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* vc4: Fix SRC_ALPHA_SATURATE blending.Eric Anholt2014-10-211-3/+11
| | | | Fixes glean blendFunc.
* vc4: Fix stencil writemask handling.Eric Anholt2014-10-211-2/+2
| | | | | | | If the writemask doesn't compress, then we want to put in the uncompressed writemask, not the compressed writemask failure value (all-on). Fixes glean's stencil2 and fbo-clear-formats on stencil.
* vc4: Don't look at back stencil state unless two-sided stencil is enabled.Eric Anholt2014-10-211-2/+6
| | | | | Fixes regressions in the next bugfix, because gallium util stuff leaves the back stencil state as 0 if !back->enabled.
* freedreno/ir3: add debug flag to disable cpRob Clark2014-10-204-1/+10
| | | | | | FD_MESA_DEBUG=nocp will disable copy propagation pass. Signed-off-by: Rob Clark <[email protected]>
* freedreno: positions come out as integers, not half-integersIlia Mirkin2014-10-201-2/+2
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: disable early-z when we have kill'sRob Clark2014-10-203-0/+10
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix potential gpu lockup with killRob Clark2014-10-204-2/+61
| | | | | | | | It seems like the hardware is unhappy if we execute a kill instruction prior to last input (ei). Probably the shader thread stops executing and the end-input flag is never set. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: comment + better fxn nameRob Clark2014-10-201-3/+5
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: only emit dirty constsRob Clark2014-10-202-5/+9
| | | | | | | | If app only updates (for example) vertex uniforms, it would be nice to only re-emit those and not also frag uniforms. Means we need to mark the first frag shader const buffer dirty after a clear. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: more layer/level fixesRob Clark2014-10-203-8/+14
| | | | Signed-off-by: Rob Clark <[email protected]>
* vc4: Translate 4-byte index buffers to 2 bytes.Eric Anholt2014-10-194-10/+92
| | | | Fixes assertion failures in 14 piglit tests (half of which now pass).
* vc4: Add support for rebasing texture levels so firstlevel == 0.Eric Anholt2014-10-195-3/+83
| | | | | | GLES2 doesn't have GL_TEXTURE_BASE_LEVEL, so the hardware doesn't. Fixes piglit levelclamp, tex-miplevel-selection, and texture-storage/2D mipmap rendering.
* vc4: Apply a Newton-Raphson step to improve RSQEric Anholt2014-10-181-2/+20
| | | | Fixes all the piglit built-in-functions/*sqrt tests, among others.
* vc4: Apply a Newton-Raphson step to improve RCP.Eric Anholt2014-10-181-1/+17
| | | | Fixes all the piglit floating-point *-op-div tests, among others.
* vc4: Add a little bit more packet parsing to make dump reading easier.Eric Anholt2014-10-181-19/+114
| | | | | Probably should have done this *before* staring at all those render lists today.
* vc4: Make some assertions about how many flushes/EOFs the simulator sees.Eric Anholt2014-10-174-9/+26
| | | | This caught the previous commit's bug in the kernel validator.
* vc4: Fix accidental dropping of the low bits of the store tilebuffer packet.Eric Anholt2014-10-171-3/+5
| | | | | | Notably this included the EOF flag (the other bits are the full buffer dump selection, but we don't do full dumps), which caused the kernel checking for frame completion to trigger.
* vc4: Set the primitive list format at the start of rendering.Eric Anholt2014-10-172-0/+15
| | | | | | | | The other driver does this manually before calling into each tile, but we can just let it get binned into the tiles (saving repeated kernel validation on the packet). Fixes simulator assertion failures on polygon-mode and non-auto texwrap.
* vc4: Replace the FLUSH_ALL with FLUSH.Eric Anholt2014-10-171-1/+3
| | | | | | We don't need to emit all of our current state at the end of each bin list. We're going to be smashing it all at the start of the next tile's bin list, anyway.
* vc4: Add some comments about state management.Eric Anholt2014-10-172-0/+11
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* vc4: Make sure there's exactly 1 tile store per tile coords packet.Eric Anholt2014-10-171-15/+64
| | | | | | It's not documented that I can see, but the other driver does it (check vg_hw_4.c), and one of the HW guys confirmed that you really do need to do it.
* vc4: correctly include the source filesEmil Velikov2014-10-162-3/+1
| | | | | | | | | The kernel files are built into a separate static library and all the functions that require it are already wrapped in ifdef USE_VC4_SIMULATOR. Don't forget the header file :) Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* freedreno/ir3: large const supportRob Clark2014-10-155-13/+33
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-10-154-5/+10
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix layer_strideRob Clark2014-10-151-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: inline fd_draw_emit()Rob Clark2014-10-152-49/+47
| | | | | | Manual LTO Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: optimize shader key comparisionRob Clark2014-10-155-40/+79
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: refactor/optimize emitRob Clark2014-10-157-83/+125
| | | | | | | | | | | | | Because we reuse various bits of emit code (for state/vertex/prog/etc) for both regular draws and internal draws (gmem<->mem, clear, etc), the number of parameters getting passed around has been growing. Refactor to group these into fd3_emit. This simplifies fxn signatures, avoids passing around shader key on the stack, etc. It also gives us a nice place to cache shader-variant lookup to avoid looking up shader variants multiple times per draw (without having to *also* pass them around as fxn args everywhere). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: refactor vertex state emitRob Clark2014-10-1511-79/+83
| | | | | | | | | | | | | | Get rid of fd3_vertex_buf and use fd_vertex_state directly for all draws. Removes a tiny bit of CPU overhead for munging around the vertex state every time it is emitted, but more importantly it cleans things up for later optimizations, so the emit paths don't have to special case internal draws (gmem<->mem, clears, etc) with regular draws. Instead of constructing fd3_vertex_buf array each time for internal draws, and context init time pre-create solid_vbuf_state and blit_vbuf_state. Signed-off-by: Rob Clark <[email protected]>
* vc4: Fix the uniform debug output.Eric Anholt2014-10-151-1/+1
| | | | | I dropped the shader index when moving to the compiled shader struct, but didn't update the format string here.
* vc4: Add support for user clip plane and gl_ClipVertex.Eric Anholt2014-10-155-4/+91
| | | | Fixes about 15 piglit tests about interpolation and clipping.
* vc4: Move the output semantics setup to a helper.Eric Anholt2014-10-151-16/+28
| | | | I want to reuse it elsewhere to set up outputs that aren't in the TGSI.
* r600g,radeonsi: Only set use_staging_texture = TRUE onceMichel Dänzer2014-10-151-8/+5
| | | | | | No need to check for setting the flag after we set it already. Reviewed-by: Marek Olšák <[email protected]>
* r600g,radeonsi: Use staging texture for transfers if any miplevel is tiledMichel Dänzer2014-10-151-1/+1
| | | | | | | We set the NO_CPU_ACCESS flag for BO allocation in that case, so direct CPU access may not work. Reviewed-by: Marek Olšák <[email protected]>
* freedreno: use tgsi_loweringRob Clark2014-10-148-1673/+6
| | | | | | | Now that the freedreno_lowering code is moved to tgsi_lowering, remove our private copy and switch over to using the common version. Signed-off-by: Rob Clark <[email protected]>
* r300/compiler: remove useless checkDavid Heidelberger2014-10-141-5/+2
| | | | | | | | This code is already in if (!variable->C->is_r500) so no need check twice. Reviewed-by: Tom Stellard <[email protected]> Signed-off-by: David Heidelberger <[email protected]>
* automake: explicitly set TARGET_RADEON_{WINSYS,COMMON}Emil Velikov2014-10-143-5/+5
| | | | | | | | | | Originally the variables were set only once via the ?= operator but that causes issues when doing incremental builds. They appear to be undefined and missing from the dependency list despite their addition to LIBADD. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84807 Signed-off-by: Emil Velikov <[email protected]>
* vc4: Fix render target NPOT alignment at small miplevels.Eric Anholt2014-10-141-3/+12
| | | | | | | | The texturing hardware takes the POT level 0 width/height and minifies those. This is different from what we were doing, for example, for 273-wide's level 5: POT(273>>5) == 8, while POT(273)>>5 == 16. Fixes piglit-depthstencil-render-miplevels 273.
* vc4: Add support for having 0 vertex elements used.Eric Anholt2014-10-142-6/+47
| | | | | You have to load at least 1, according to the simulator. Fixes 4 piglit tests and even more ES2 conformance tests.
* ilo: clear writer pointer after unmappingChia-I Wu2014-10-141-0/+1
| | | | | | | It does not look like an issue now but it is good to be future proof. Spotted by Courtney Goeltzenleuchter. Signed-off-by: Chia-I Wu <[email protected]>
* vc4: Write the VPM read setup multiple times to queue all the inputs.Eric Anholt2014-10-131-3/+18
| | | | | | | There's a 4-element fifo, and the size (number of dwords per vertex) field is just 4 bits. Fixes glsl-routing on sim.
* vc4: Add support for the TXL opcode.Eric Anholt2014-10-131-5/+15
| | | | | | There's a bit at the bottom of cube map stride (which has some formatting bugs in the docs) which flips the bias coordinate to being an absolute LOD.
* vc4: Improve the accuracy of SIN and COS.Eric Anholt2014-10-131-11/+17
| | | | | | | | | This gets them to pass glsl-sin/cos. There was an obvious problem that I was using the FRC code on the scaled input value, which means that we had a range in [0, 1], while our taylor is most accurate across [-0.5, 0.5]. We can just slide things over, but that means flipping the sign of the coefficients. After that, it was just a matter of stuffing more coefficients in.
* vc4: Match VS outputs to FS inputs.Eric Anholt2014-10-133-18/+135
| | | | | | | | | If the VS doesn't output a value that the FS needs, we still need to read the right contents for the remaining FS inputs, by emitting padding. And if the VS outputs something the FS doesn't need, we shouldn't put it in the VPM at all (so the code producing it can get DCEed). Fixes 77 piglit tests.
* vc4: Add support for the CEIL opcode.Eric Anholt2014-10-131-0/+22
| | | | Not as big of a deal as SSG, but still +9 piglit tests.
* vc4: Add support for the SSG opcode.Eric Anholt2014-10-131-0/+12
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* r600g: Implement GL_ARB_sample_shadingGlenn Kennard2014-10-1210-119/+383
| | | | | | | | Also fixes two sided lighting which was broken at least on pre-evergreen by commit b1eb00. Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: use tgsi_shader_info in si_llvm_emit_fs_epilogueMarek Olšák2014-10-121-71/+61
| | | | | | | | | This is the last use tgsi_parse_token in radeonsi. It looks ugly because the code was re-indented, but there is really no change in behavior. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove si_shader_output_values::indexMarek Olšák2014-10-121-17/+6
| | | | | | | | It's redundant now. It led to a simplification in si_llvm_emit_streamout, because outidx == reg. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: use tgsi_shader_info in si_llvm_emit_vs_epilogueMarek Olšák2014-10-121-26/+13
| | | | | | That code was really ugly. Reviewed-by: Michel Dänzer <[email protected]>
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