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| * gallium: add void *user_buffer in pipe_index_bufferMarek Olšák2012-04-3018-63/+74
| | | | | | | | | | | | | | Adapted drivers: i915, llvmpipe, r300, r600, radeonsi, softpipe. User index buffers have been disabled in nv30, nv50, nvc0 and svga to keep things working.
| * gallium: remove pipe_context::redefine_user_bufferMarek Olšák2012-04-3018-109/+0
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| * gallium: add void *user_buffer in pipe_vertex_bufferMarek Olšák2012-04-309-11/+26
| | | | | | | | | | | | | | | | | | | | | | | | This reduces CPU overhead in st_draw_vbo and removes a lot of unnecessary code in that function which was required only to comply with the gallium interface, but wasn't any useful really. Adapted drivers: i915, llvmpipe, r300, softpipe. No changes required in: r600, radeonsi. User vertex buffers have been disabled in nv30, nv50, nvc0 and svga to keep things working.
| * gallium: change set_constant_buffer to be UBO-friendlyMarek Olšák2012-04-3019-74/+87
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| * gallium: add PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENTMarek Olšák2012-04-3010-0/+24
| | | | | | | | | | | | | | | | This is required for any serious constant buffer support. Constant buffer offsets on ATI and NVIDIA DX10 and DX11 GPUs must be a multiple of 256. In OpenGL, this can be queried via GL_UNIFORM_BUFFER_OFFSET_ALIGNMENT.
| * gallium: add PIPE_CAP_USER_INDEX_BUFFERS and PIPE_CAP_USER_CONSTANT_BUFFERSMarek Olšák2012-04-3010-0/+20
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* | gallium/tgsi: s/TGSI_BUFFER/TGSI_TEXTURE_BUFFER/José Fonseca2012-05-111-2/+1
| | | | | | | | | | | | For consistency. Reviewed-by: Brian Paul <[email protected]>
* | gallium/tgsi: Redefine the TGSI_TEXTURE_UNKNOWN texture target.José Fonseca2012-05-111-0/+2
| | | | | | | | | | | | | | | | | | Some code relies on the existing of an invalid texture target. It seems safer to bring it back than to deal with unintended consequences. This partially reverts commit a4ebb04214bab1cd9bd41967232ec89441e31744. Reviewed-by: Brian Paul <[email protected]>
* | llvmpipe: Fix triangle bounding box calculation to be correctly inclusive or ↵James Benton2012-05-111-8/+6
| | | | | | | | | | | | | | | | exclusive Tested with custom rasterisation test tool added to piglit suite, reduced errors Signed-off-by: José Fonseca <[email protected]>
* | llvmpipe: Change triangle rasterization comparison from < 0 to <= 0James Benton2012-05-111-1/+8
| | | | | | | | | | | | Tested with custom rasterisation test tool added to piglit suite, reduced errors Signed-off-by: José Fonseca <[email protected]>
* | gallium/tgsi: Define the TGSI_BUFFER texture target.Francisco Jerez2012-05-111-2/+2
| | | | | | | | | | | | This texture type was already referred to by the documentation but it was never defined. Define it as 0 to match the pipe_texture_target enumeration values.
* | gallium/tgsi: Move interpolation info from tgsi_declaration to a separate token.Francisco Jerez2012-05-114-10/+11
| | | | | | | | | | | | Move Interpolate, Centroid and CylindricalWrap from tgsi_declaration to a separate token -- they only make sense for FS inputs and we need room for other flags in the top-level declaration token.
* | gallium/tgsi: Split sampler views from shader resources.Francisco Jerez2012-05-112-25/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit splits the current concept of resource into "sampler views" and "shader resources": "Sampler views" are textures or buffers that are bound to a given shader stage and can be read from in conjunction with a sampler object. They are analogous to OpenGL texture objects or Direct3D SRVs. "Shader resources" are textures or buffers that can be read and written from a shader. There's no support for floating point coordinates, address wrap modes or filtering, and, unlike sampler views, shader resources are global for the whole graphics pipeline. They are analogous to OpenGL image objects (as in ARB_shader_image_load_store) or Direct3D UAVs. Most hardware is likely to implement shader resources and sampler views as separate objects, so, having the distinction at the API level simplifies things slightly for the driver. This patch introduces the SVIEW register file with a declaration token and syntax analogous to the already existing RES register file. After this change, the SAMPLE_* opcodes no longer accept a resource as input, but rather a SVIEW object. To preserve the functionality of reading from a sampler view with integer coordinates, the SAMPLE_I(_MS) opcodes are introduced which are similar to LOAD(_MS) but take a SVIEW register instead of a RES register as argument.
* | radeonsi: Properly translate vertex format swizzle.Michel Dänzer2012-05-113-23/+23
| | | | | | | | egltri_screen works correctly!
* | radeon/llvm: Remove AMDILMCCodeEmitter.cppTom Stellard2012-05-102-158/+0
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* | radeon/llvm: Remove SILowerShaderInstructions.cppTom Stellard2012-05-104-81/+0
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* | radeonsi/llvm: Move lowering of RETURN to ConvertToISA passTom Stellard2012-05-102-11/+2
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* | radeon/llvm: Add some commentsTom Stellard2012-05-1064-422/+393
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* | radeon/llvm: Move util functions into AMDGPU namespaceTom Stellard2012-05-103-39/+37
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* | radeon/llvm: Auto-encode RAT_WRITE_CACHELESS_egTom Stellard2012-05-102-17/+0
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* | radeon/llvm: Delete all instructions that have been custom loweredTom Stellard2012-05-101-4/+1
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* | radeonsi: Set NONE format for unused vertex shader position export slots.Michel Dänzer2012-05-101-3/+3
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* | radeonsi: Eliminate one more magic number for texture image resources.Michel Dänzer2012-05-101-3/+3
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* | radeonsi: Fix vertex buffer resource for stride 0.Michel Dänzer2012-05-101-1/+5
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* | radeon/llvm: Remove AMDGPUConstants.pmTom Stellard2012-05-092-45/+23
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* | radeon/llvm: Don't rely on tablegen for lowering int_AMDGPU_load_constTom Stellard2012-05-095-38/+20
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* | radeon/llvm: Make sure the LOAD_CONST def uses the isSI predicateTom Stellard2012-05-092-7/+7
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* | svga: implement CEIL opcode translationBrian Paul2012-05-091-0/+28
| | | | | | | | Reviewed-by: José Fonseca <[email protected]>
* | gallium/drivers: handle TGSI_OPCODE_CEILChristoph Bumiller2012-05-094-0/+28
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* | r600g: Handle TGSI_OPCODE_CEIL (v2)Kai Wasserbäch2012-05-091-3/+3
| | | | | | | | | | | | | | v2: Enabled CEIL on Cayman too. Signed-off-by: Kai Wasserbäch <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* | radeon/llvm: Remove AMDILUtilityFunctions.cppTom Stellard2012-05-0813-1041/+399
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* | radeon/llvm: Remove some unused functions from AMDILInstrInfoTom Stellard2012-05-082-164/+0
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* | radeon/llvm: Add some comments and fix coding styleTom Stellard2012-05-088-42/+41
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* | radeon/llvm: Remove the EXPORT_REG instructionTom Stellard2012-05-0810-117/+8
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* | radeon/llvm: Use a custom inserter to lower RESERVE_REGTom Stellard2012-05-0810-27/+83
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* | radeon/llvm: Use a custom inserter to lower STORE_OUTPUTTom Stellard2012-05-084-34/+23
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* | radeon/llvm: Remove AMDGPULowerShaderInstructions classTom Stellard2012-05-086-86/+4
| | | | | | | | It is no longer used.
* | radeon/llvm: Use a custom inserter to lower LOAD_INPUTTom Stellard2012-05-084-39/+15
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* | radeon/llvm: Remove the ReorderPreloadInstructions passTom Stellard2012-05-089-100/+4
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* | radeon/llvm: Remove old comment from AMDIL.hTom Stellard2012-05-081-5/+0
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* | radeon/llvm: add suport for cube texturesVadim Girlin2012-05-082-23/+91
| | | | | | | | Signed-off-by: Vadim Girlin <[email protected]>
* | radeon/llvm: add support for CUBE ALU instructionVadim Girlin2012-05-085-21/+63
| | | | | | | | Signed-off-by: Vadim Girlin <[email protected]>
* | radeon/llvm: add support for some ALU instructionsVadim Girlin2012-05-084-13/+293
| | | | | | | | | | | | | | | | Add support for IABS, NOT, AND, XOR, OR, UADD, UDIV, IDIV, MOD, UMOD, INEG, I2F, U2F, F2U, F2I, USEQ, USGE, USLT, USNE, ISGE, ISLT, ROUND, MIN, MAX, IMIN, IMAX, UMIN, UMAX Signed-off-by: Vadim Girlin <[email protected]>
* | radeon/llvm: add missing cases for BREAK/CONTINUEVadim Girlin2012-05-082-0/+3
| | | | | | | | Signed-off-by: Vadim Girlin <[email protected]>
* | radeon/llvm: add support for AHSR/LSHR/LSHL instructionsVadim Girlin2012-05-084-0/+53
| | | | | | | | Signed-off-by: Vadim Girlin <[email protected]>
* | radeon/llvm: add support for TXQ/TXF/DDX/DDY instructionsVadim Girlin2012-05-085-4/+43
| | | | | | | | Signed-off-by: Vadim Girlin <[email protected]>
* | radeon/llvm: add support for VertexID, InstanceIDVadim Girlin2012-05-083-0/+50
| | | | | | | | Signed-off-by: Vadim Girlin <[email protected]>
* | radeon/llvm: fix live-in handling for inputsVadim Girlin2012-05-082-2/+3
| | | | | | | | | | | | Set the input registers as live-in for entry basic block. Signed-off-by: Vadim Girlin <[email protected]>
* | radeon/llvm: add support for v4i32Vadim Girlin2012-05-084-5/+20
| | | | | | | | Signed-off-by: Vadim Girlin <[email protected]>
* | radeon/llvm: fix ABS_i32 instruction loweringVadim Girlin2012-05-081-2/+2
| | | | | | | | | | | | Swap source operands. Signed-off-by: Vadim Girlin <[email protected]>
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