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* r600g: move streamout state to drivers/radeonMarek Olšák2013-08-3127-1486/+1825
| | | | | | | | | | | | | | | | | | | | | | | | This streamout state code will be used by radeonsi. There are new structures r600_common_context and r600_common_screen. What is inherited by what is shown here: pipe_context -> r600_common_context -> r600_context pipe_screen -> r600_common_screen -> r600_screen The common structures reside in drivers/radeon. Currently they only contain enough functionality to be able to handle streamout. Eventually I'd like the whole pipe_screen implementation to be shared and some of the context stuff too. This is quite big, but most changes are because of the new structures and the fact r600_write_value is replaced by radeon_emit. Thanks to Tom Stellard for fixing the build for r600g/compute. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-by: Tom Stellard <[email protected]>
* radeonsi: cleanup initialization of SGPR shader parametersMarek Olšák2013-08-311-13/+19
| | | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-by: Tom Stellard <[email protected]>
* r600g,radeonsi: remove unused variablesMarek Olšák2013-08-312-8/+0
| | | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-by: Tom Stellard <[email protected]>
* radeonsi: Do not suspend timer queriesNiels Ole Salscheider2013-08-306-14/+30
| | | | | Signed-off-by: Niels Ole Salscheider <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* softpipe: handle NULL sampler views for texture sampling / queriesRoland Scheidegger2013-08-301-5/+25
| | | | | | | Instead of crashing just return all zero. Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Zack Rusin <[email protected]>
* softpipe: check if so_target is NULL before accessing itRoland Scheidegger2013-08-301-2/+5
| | | | | | | | | | No idea if this is working right but copied straight from llvmpipe. (Not only does this check the so_target but also use buffer->data instead of buffer for the mapping.) Just trying to get rid of a segfault testing something else... Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Zack Rusin <[email protected]>
* r600g: enable SB backend by defaultVadim Girlin2013-08-304-5/+6
| | | | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Christian König <[email protected]>
* r600g: fix color exports when we have no CBsVadim Girlin2013-08-301-3/+4
| | | | | | | We need to export at least one color if the shader writes it, even when nr_cbufs==0. Signed-off-by: Vadim Girlin <[email protected]>
* nvc0/ir: Initialize NVC0LegalizePostRA member variables.Vinson Lee2013-08-291-1/+3
| | | | | | Fixes "Uninitialized pointer field" defects reported by Coverity. Signed-off-by: Vinson Lee <[email protected]>
* radeonsi: Early return if no depth or stencil on release builds.Vinson Lee2013-08-291-0/+1
| | | | | | | Fixes "Missing break in switch" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* freedreno: updates for msm drm/kms driverRob Clark2013-08-298-30/+55
| | | | | | | There where some small API tweaks in libdrm_freedreno to enable support for msm drm/kms driver. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: handle sync flags betterRob Clark2013-08-291-16/+34
| | | | | | | | We need to set the flag on all the .xyzw components that are written by the instruction, not just on .x. Otherwise a later use of rN.y (for example) will not trigger the appropriate sync bit to be set. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: better const handlingRob Clark2013-08-291-90/+121
| | | | | | | | | Seems like most/all instructions have some restrictions about const src registers. In seems like the 2 src (cat2) instructions can take at most one const, and the 3 src (cat3) instructions can take at most one const in the first 2 arguments. And so on. Handle this properly now. Signed-off-by: Rob Clark <[email protected]>
* radeonsi: Make sure libdrm_radeon headers are picked up from the right placeJonathan Gray2013-08-291-1/+2
| | | | | | And remove libdrm/ from a winsys include statement. Signed-off-by: Jonathan Gray <[email protected]>
* radeon/uvd: fix MPEG2/4 ref frame index limitChristian König2013-08-291-2/+2
| | | | | | Otherwise the first few frames have an incorrect reference index. Signed-off-by: Christian König <[email protected]>
* nouveau: Copy m4x4 and m8x8 separately.Vinson Lee2013-08-281-1/+2
| | | | | | Silences Coverity "Out-of-bounds access" defect. Signed-off-by: Vinson Lee <[email protected]>
* r300g: enable MSAA on r300-r400, be careful about using color compressionMarek Olšák2013-08-274-5/+14
| | | | | | | | | | MSAA was tested by one user on RS690 and it works for him with color compression (CMASK) disabled. Our theory is that his chipset lacks CMASK RAM. Since we don't have hardware documentation about which chipsets actually have CMASK RAM, I had to take a guess based on the presence of HiZ. Reviewed-by: Alex Deucher <[email protected]>
* draw: clean up setting stream out information a bitRoland Scheidegger2013-08-276-29/+37
| | | | | | | | | | | | | | | | | In particular noone is interested in the vertex count, so drop that, and also drop the duplicated num_primitives_generated / so.primitives_storage_needed variables in drivers. I am unable for now to figure out if primitives_storage_needed in SO stats (used for d3d10) should increase if SO is disabled, though the equivalent num_primitives_generated used for OpenGL definitely should increase. In any case we were only counting when SO is active both in softpipe and llvmpipe anyway so don't pretend there's an independent num_primitives_generated counter which would count always. (This means the PIPE_QUERY_PRIMITIVES_GENERATED count will still be wrong just as before, should eventually fix this by doing either separate counting for this query or adjust the code so it always counts this even if SO is inactive depending on what's correct for d3d10.) Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: support nested/overlapping queries for all query typesRoland Scheidegger2013-08-273-18/+20
| | | | | | | There's just no way resetting the counters is working with nested/overlapping queries. Reviewed-by: Brian Paul <[email protected]>
* softpipe: support nested/overlapping queries for all query typesRoland Scheidegger2013-08-272-18/+17
| | | | | | | There's just no way resetting the counters is working with nested/overlapping queries. Reviewed-by: Brian Paul <[email protected]>
* svga: replace 0 with PIPE_OK in a few placesBrian Paul2013-08-263-5/+5
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* radeonsi: Also set the depth component mask bit for stencil-only exportsMichel Dänzer2013-08-261-1/+4
| | | | | | | | The stencil values come out wrong without this for some reason. 50 more little piglits. Cc: [email protected]
* r600g: Implement the new float comparison instructions for Cayman as well.Henri Verbeet2013-08-251-4/+4
| | | | | | | | I assume this should have been part of commit 7727fbb7c5d64348994bce6682e681d6181a91e9. This (obviously) fixes a lot tests. Signed-off-by: Henri Verbeet <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nv30: add forgotten PIPE_CAP_CUBE_MAP_ARRAY cap to listIlia Mirkin2013-08-251-0/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "9.2" <[email protected]>
* nouveau/video: avoid overwriting base codec init with templateIlia Mirkin2013-08-252-2/+2
| | | | | | | | | | Commit 53e20b8b introduced the use of a template to initialize some common fields. Move this copying of fields to before the common vp3 fields are initialized. Reported-by: Martin Peres <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Christian König <[email protected]>
* freedreno/a3xx: don't leak so muchRob Clark2013-08-241-0/+11
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: fix SGT/SLT/etcRob Clark2013-08-241-29/+125
| | | | | | | | | | The cmps.f.* instruction doesn't actually seem to give a float 1.0 or 0.0 output. It either needs a cov.u16f16 or add.s + sel.f16. This makes SGT/SLT/etc more similar to CMP, so handle them in trans_cmp(). This fixes a bunch of piglit tests. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: bit of re-arrange/cleanupRob Clark2013-08-241-61/+71
| | | | | | | | It seems there are a number of cases where instructions have limitations about taking reading src's from const register file, so make get_unconst() a bit easier to use. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: make compiler errors more usefulRob Clark2013-08-242-17/+33
| | | | | | | | | | | | | | We probably should get rid of assert() entirely, but at this stage it is more useful for things to crash where we can catch it in a debugger. With compile_error() we have a single place to set an error flag (to bail out and return an error on the next instruction) so that will be a small change later when enough of the compiler bugs are sorted. But re-arrange/cleanup the error/assert stuff so we at least get a dump of the TGSI that triggered it. So we see some useful output in piglit logs. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix segfault when no color buffer boundRob Clark2013-08-247-18/+40
| | | | | | | Don't crash when no color buffer bound. Something caught when starting to run piglit, fixes a hanful of piglit tests. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: cat4 cannot use const reg as srcRob Clark2013-08-241-10/+27
| | | | | | | | | | | | | Category 4 instructions (rsq, rcp, sqrt, etc) seem to be unable to take a const register as src. In these cases we need to move the src to a temporary gpr first. This is the second case of such a restriction, where the instruction encoding appears to support a const src, but in fact the hw appears to ignore that bit. So split things out into a helper that can be re-used for any instructions which have this limitation. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: use max_reg rather than file_countRob Clark2013-08-241-7/+7
| | | | | | | | | | Our current (rather naive) register assignment is based on mapping different register files (INPUT, OUTPUT, TEMP, CONST, etc) based on the max register index of the preceding file. But in some cases, the lowest used register in a file might not be zero. In which case file_count[file] != file_max[file] + 1. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: handle saturate on dstRob Clark2013-08-241-0/+49
| | | | | | | | Sometimes things other than color dst need saturating, like if there is a 'clamp(foo, 0.0, 1.0)'. So for saturated dst add the extra instructions to fix up dst. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: fix CMPRob Clark2013-08-241-2/+2
| | | | | | | | | | | | | | | | The 1st src to add.s needs (r) flag (repeat), otherwise it will end up: add.s dst.xyzw, tmp.xxxx -1 instead of: add.s dst.xyzw, tmp.xyzw, -1 Also, if we are using a temporary dst to avoid clobbering one of the src registers, we actually need to use that as the dst for the sel instruction. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: some texture fixesRob Clark2013-08-241-1/+24
| | | | | | Stop hard coding bits that indicate texture type (2d/3d/cube/etc). Signed-off-by: Rob Clark <[email protected]>
* freedreno: update register headersRob Clark2013-08-248-111/+758
| | | | | | resync w/ rnndb database Signed-off-by: Rob Clark <[email protected]>
* freedreno: add debug option to disable scissor optimizationRob Clark2013-08-243-14/+22
| | | | | | Useful for testing and debugging. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix viewport on gmem->mem resolveRob Clark2013-08-241-0/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix color inversion on mem->gmem restoreRob Clark2013-08-241-3/+3
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeonsi: Handle additional PIPE_COMPUTE_CAP_*Niels Ole Salscheider2013-08-231-1/+14
| | | | | | | | | | | This patch adds support for: PIPE_COMPUTE_CAP_MAX_INPUT_SIZE PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE Return the values reported by the closed source driver for now. Signed-off-by: Niels Ole Salscheider <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: copy r600_get_timestampNiels Ole Salscheider2013-08-231-0/+9
| | | | | Signed-off-by: Niels Ole Salscheider <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Implement PIPE_QUERY_TIMESTAMPNiels Ole Salscheider2013-08-234-2/+46
| | | | | Signed-off-by: Niels Ole Salscheider <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Fix y/z/w component values of TGSI_SEMANTIC_FOG pixel shader inputsMichel Dänzer2013-08-221-0/+18
| | | | | | | | | They are defined as constant 0.0/0.0/1.0. Three more little piglits. Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* trace: Handle null tokens.José Fonseca2013-08-221-2/+6
| | | | Used for example on stream out without geometry shader.
* ilo: do not need last shader stage for 3DSTATE_SBEChia-I Wu2013-08-224-14/+6
| | | | | | We have set up 3DSTATE_SBE (or 3DSTATE_SF on GEN6) in ilo_shader_select_kernel_routing(). There is no need to pass the last shader stage to the GPE function.
* ilo: fix a potential issue with STATE_SIPChia-I Wu2013-08-221-2/+2
| | | | | Command length is ORed to the wrong place. Since the ORed value is zero, there is no real change.
* ilo: add GEN check to 3DSTATE_CLIPChia-I Wu2013-08-221-0/+2
| | | | Assert that gen6_emit_3DSTATE_CLIP is for GEN 6 and 7.
* svga: minor clean-ups in emit_hw_vs_vdecl()Brian Paul2013-08-211-6/+6
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* gallivm: implement better control of per-quad/per-element/scalar lodRoland Scheidegger2013-08-201-4/+4
| | | | | | | | | | | | | | | | There's a new debug value used to disable per-quad lod optimizations in fragment shader (ignored for vs/gs as the results are just too wrong typically). Also trying to detect if a supplied lod value is really a scalar (if it's coming from immediate or constant file) in which case sampler code can use this to stay on per-quad-lod path (in fact for explicit lod could simplify even further and use same lod for both quads in the avx case but this is not implemented yet). Still need to actually implement per-element lod bias (and derivatives), and need to handle per-element lod in size queries. v2: fix comments, prettify. Reviewed-by: Jose Fonseca <[email protected]>
* radeonsi: Always pre-load separate VGPRs for centroid vs. center interpolationMichel Dänzer2013-08-201-1/+2
| | | | | | | | | | | | | The LLVM R600 backend currently always uses separate VGPRs for these. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68162 (Centroid interpolation is identical to center interpolation without multisampling, so the shader hardware was only pre-loading one set of interpolation coefficients, and the pixel shader code was using uninitialized values as the centroid interpolation coefficients) Cc: [email protected] Tested-by: Laurent Carlier <[email protected]>
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