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* radeonsi: clear allocator_zeroed_memory with SDMAMarek Olšák2019-02-064-12/+9
| | | | | | | | so that it can be used in parallel IBs. This also removes the SO_FILLED_SIZE hack. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: initialize textures using DCC to black when possibleMarek Olšák2019-02-063-13/+63
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* freedreno: a2xx: fix fast clearJonathan Marek2019-02-061-1/+0
| | | | | | | Fixes: 912a9c8d Signed-off-by: Jonathan Marek <[email protected]> Cc: 19.0 <[email protected]>
* v3d: Store the actual mask of color buffers present in the key.Eric Anholt2019-02-051-9/+10
| | | | | | | If you only bound rt 1+, we'd still emit a write to the rt0 that isn't present (noticed while debugging an ext_framebuffer_multisample-alpha-to-coverage-no-draw-buffer-zero regression in another change).
* v3d: Fix precompile of FRAG_RESULT_DATA1 and higher outputs.Eric Anholt2019-02-051-1/+1
| | | | I was just leaving the other MRT targets than DATA0 out, by accident.
* nir: Move V3D's "the shader was TGSI, ignore FS output types" flag to NIR.Eric Anholt2019-02-052-10/+2
| | | | | | | | | | | | | | Ken's rework of mesa/st builtins to NIR means that we'll have more NIR shaders with color output types that are mismatched with the render target types. Since this is behavior that GLSL doesn't require, add it as a shader_info option so the driver can know that it needs to ignore the FS output's base type in favor of the actual render target's. This prevents needing additional variants in several mesa/st paths (clear, pbo upload, pbo download), given that the driver already has to handle the variants for any TGSI being passed to it (from u_blitter, for example). Reviewed-by: Rob Clark <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nvc0/ir: replace cvt instructions with add to improve shader performanceKarol Herbst2019-02-052-0/+64
| | | | | | | | | | | | | | | | | | | gives me an performance boost of 0.2% in pixmark_piano on my gk106, gm204 and gp107. reduces the amount of generated convert instructions by roughly 30% in shader-db. v2: only for 32 bit operations move some common code out of the switch handle OP_SAT with modifiers v3: only for registers and const memory rework if clauses merge isCvt into this patch v4: merge isCvt into its use Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* swr/rast: update SWR rasterizer shader statsAlok Hota2019-02-0510-38/+204
| | | | | | Primarily refactoring internal stats types Reviewed-by: Bruce Cherniak <[email protected]>
* radeonsi: release tokens after creating the shader programGert Wollny2019-02-051-0/+2
| | | | | | | | | | | | | | | | | | | | ureg_get_tokens clears the reference to the tokens, and create_compute_state makes a copy, hence the tokens must be explicitely released. Fixes: Direct leak of 256 byte(s) in 1 object(s) allocated from: #0 0x7ff729cf3c60 in realloc (/usr/lib64/gcc/x86_64-pc-linux-gnu/7.3.0/libasan.so+0xdbc60) #1 0x7ff721b1240c in tokens_expand ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:234 #2 0x7ff721b1c9c0 in get_tokens ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:257 #3 0x7ff721b1c9c0 in copy_instructions ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:2040 #4 0x7ff721b1c9c0 in ureg_finalize ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:2090 #5 0x7ff721b1e919 in ureg_get_tokens ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:2167 #6 0x7ff721f8b35a in si_create_dma_compute_shader ../../samba/mesa/src/gallium/drivers/radeonsi/si_shaderlib_tgsi.c:219 #7 0x7ff722043ed9 in si_compute_do_clear_or_copy ../../samba/mesa/src/gallium/drivers/radeonsi/si_compute_blit.c:156 #8 0x7ff7220448d3 in si_clear_buffer ../../samba/mesa/src/gallium/drivers/radeonsi/si_compute_blit.c:247 #9 0x7ff7220350e8 in vi_dcc_clear_level ../../samba/mesa/src/gallium/drivers/radeonsi/si_clear.c:274 Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nv50,nvc0: add explicit settings for recent capsIlia Mirkin2019-02-042-0/+4
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: 19.0 <[email protected]>
* panfrost: Implement Midgard shader toolchainAlyssa Rosenzweig2019-02-0513-2/+6383
| | | | | | | | | | | | | | | This patch implements the free Midgard shader toolchain: the assembler, the disassembler, and the NIR-based compiler. The assembler is a standalone inaccessible Python script for reference purposes. The disassembler and the compiler are implemented in C, accessible via the standalone `midgard_compiler` binary. Later patches will use these interfaces from the driver for online compilation. Signed-off-by: Alyssa Rosenzweig <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Rob Clark <[email protected]> Acked-by: Eric Anholt <[email protected]> Acked-by: Emil Velikov <[email protected]>
* panfrost: Initial stub for Panfrost driverAlyssa Rosenzweig2019-02-0511-0/+2984
| | | | | | | | | | | | | This patch adds an initial stub for the Gallium driver, containing simple screen functions and the majority of the driver headers but no actual functionality. It further adds the winsys glue for linking in this stub driver via kmsro on Rockchip/Amlogic boards. Signed-off-by: Alyssa Rosenzweig <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Rob Clark <[email protected]> Acked-by: Eric Anholt <[email protected]> Acked-by: Emil Velikov <[email protected]>
* radeonsi: fix crashing performance counters (division by zero)Marek Olšák2019-02-041-1/+1
| | | | Fixes: e2b9329f17 "radeonsi: move remaining perfcounter code into si_perfcounter.c"
* radeonsi: handle render_condition_enable in si_compute_clear_render_targetMarek Olšák2019-02-043-3/+8
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* radeonsi: use compute for clear_render_target when possibleSonny Jiang2019-02-045-0/+184
| | | | | Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* ac/radv/radeonsi: add ac_get_num_physical_sgprs() helperTimothy Arceri2019-02-011-4/+3
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* freedreno: more fixing release tarballRob Clark2019-01-311-1/+3
| | | | | Fixes: aa0fed10d35 freedreno: move ir3 to common location Signed-off-by: Rob Clark <[email protected]>
* virgl: ARB_query_buffer_object supportDave Airlie2019-01-317-1/+58
| | | | | | v1.1: fix size define. Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: enable elapsed time queriesDave Airlie2019-01-311-1/+1
| | | | | | GL underneath always has GL_TIME_ELAPSED so always enable these. Reviewed-by: Gurchetan Singh <[email protected]>
* radeonsi: fix a comment typo in si_fine_fence_setMarek Olšák2019-01-301-1/+1
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* r600: add -Wstrict-overflow=0 to meson to silence the warningMarek Olšák2019-01-301-1/+1
| | | | same as radeonsi
* radeonsi: unify error paths in si_texture_create_objectMarek Olšák2019-01-301-9/+9
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* radeonsi: merge & rename texture BO metadata functionsMarek Olšák2019-01-301-64/+53
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* radeonsi: enable dithered alpha-to-coverage for better qualityMarek Olšák2019-01-301-4/+5
| | | | | | | same as AMDVLK. GL_NV_alpha_to_coverage_dither_control allows controlling this behavior. The default is implementation-dependent.
* v3d: Fix leak in resource setup error pathErnestas Kulik2019-01-291-1/+1
| | | | | | | | | Reported by Coverity: in the case of unsupported modifier request, the code does not jump to the “fail” label to destroy the acquired resource. CID: 1435704 Signed-off-by: Ernestas Kulik <[email protected]> Fixes: 45bb8f295710 ("broadcom: Add V3D 3.3 gallium driver called "vc5", for BCM7268.")
* vc4: Fix leak in HW queries error pathErnestas Kulik2019-01-291-1/+1
| | | | | | | | | | Reported by Coverity: in the case where there exist hardware and non-hardware queries, the code does not jump to err_free_query and leaks the query. CID: 1430194 Signed-off-by: Ernestas Kulik <[email protected]> Fixes: 9ea90ffb98fb ("broadcom/vc4: Add support for HW perfmon")
* v3d: Always enable the NEON utile load/store code.Eric Anholt2019-01-291-5/+6
| | | | | | | I can't imagine the new HW block being paired with a v6 CPU, so don't bother with the CPU detection that vc4 had to do. Improves 1024x1024 TexImage on my 7278 by 47.3229% +/- 0.679632%
* freedreno: fix sysmem rendering being used when clear is usedJonathan Marek2019-01-291-1/+1
| | | | | | | | | | This batch->cleared value is only used to decide to use sysmem rendering or not, so it should include any buffers that are affected by a clear. This is required because the a2xx fast clear doesn't work with sysmem rendering. The a22x "normal" clear path doesn't work with sysmem either. Signed-off-by: Jonathan Marek <[email protected]>
* freedreno: fix depth usage logicJonathan Marek2019-01-291-2/+6
| | | | | | | | Depth can be used even when there is no restore/resolve of depth. This happens when the depth buffer is invalidated after rendering to avoid the resolve operation. Signed-off-by: Jonathan Marek <[email protected]>
* freedreno: fix invalidate logicJonathan Marek2019-01-292-10/+10
| | | | | | | | Set dirty bits on invalidate to trigger invalidate logic in fd_draw_vbo. Also, resource_written for color needs to be after the invalidate logic. Signed-off-by: Jonathan Marek <[email protected]>
* freedreno: minor cleanupsRob Clark2019-01-292-2/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: stop frob'ing pipe_resource::nr_samplesRob Clark2019-01-294-6/+15
| | | | | | | | | | | | Previously we tried to normalize nr_samples to MAX2(1, nr_samples) to avoid having to deal with 0 vs 1 everywhere. But this causes problems in mesa/st, for example st_finalize_texture() will think there is a nr_samples mismatch and recreate the texture. Somehow this manifests as corrupt x11 font rendering on generations that do not support MSAA (but apparently works fine on a5xx and a6xx which do support MSAA.) Fixes: cf0c7258ee0 freedreno/a5xx: MSAA Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: fix blitter nr_samples checkRob Clark2019-01-291-1/+3
| | | | | | nr_samples for non-MSAA case could be either zero or one. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: fix blitter nr_samples checkRob Clark2019-01-291-1/+2
| | | | | | nr_samples for non-MSAA case could be either zero or one. Signed-off-by: Rob Clark <[email protected]>
* vc4: Enable NEON asm on meson cross-builds.Eric Anholt2019-01-281-4/+6
| | | | | | | | | The core Mesa with_asm_arch and USE_ARM_ASM flags are disabled for meson cross-builds because of the need to run host binaries on the build system. vc4 doesn't need to do that, so skip with_asm_arch to enable NEON on my cross-builds. Fixes: ebcb4c2156e9 ("meson: Enable VC4's NEON assembly support.")
* freedreno: a2xx: add perfcntrsJonathan Marek2019-01-288-0/+1118
| | | | | | Based on a5xx perfcntrs implementation. Signed-off-by: Jonathan Marek <[email protected]>
* freedreno: a2xx: minor solid_vertexbuf fixupsJonathan Marek2019-01-283-4/+6
| | | | | | | The big thing here is the 0x60 offset for the mem2gmem copy which I missed in my last patch. Signed-off-by: Jonathan Marek <[email protected]>
* freedreno: a2xx: clear fixes and fast clear pathJonathan Marek2019-01-288-126/+434
| | | | | | | | This fixes the depth/stencil clear on a20x, and adds a fast clear path. The fast clear path is only used for a20x, needs performance tests on a22x. Signed-off-by: Jonathan Marek <[email protected]>
* freedreno: a2xx: a20x hw binningJonathan Marek2019-01-2811-16/+298
| | | | Signed-off-by: Jonathan Marek <[email protected]>
* freedreno: a2xx: enable early-Z testingJonathan Marek2019-01-284-3/+11
| | | | | | | Enable earlyZ when alpha test is disabled. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno: a2xx: ir2 cleanupJonathan Marek2019-01-282-3/+1
| | | | Reviewed-by: Rob Clark <[email protected]>
* Switch imx to kmsro and remove the imx winsysRob Herring2019-01-283-17/+1
| | | | | | | The kmsro winsys is equivalent to the imx winsys, so we can switch to it and remove the imx one. Signed-off-by: Rob Herring <[email protected]>
* kmsro: Extend to include hx8357d.Eric Anholt2019-01-282-0/+2
| | | | | | | | | | | | This allows vc4 to initialize on the Adafruit PiTFT 3.5" touchscreen with the hx8357d tinydrm driver v2: Whitespace fix noted by Eric Engestrom, update commit message for the driver being merged. v3: Rebase on Rob Herring's pipe-loader changes. Acked-by: Eric Engestrom <[email protected]> (v1) Acked-by: Emil Velikov <[email protected]> (v1)
* pl111: Rename the pl111 driver to "kmsro".Eric Anholt2019-01-285-14/+14
| | | | | | | | | | | | The vc4 driver can do prime sharing to many different KMS-only devices, such as the various tinydrm drivers for SPI-attached displays. Rename the driver away from "pl111" to represent what it will actually support: various sorts of KMS displays with the renderonly layer used to attach a GPU. Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> Acked-by: Emil Velikov <[email protected]>
* virgl: Set sRGB write control CAP based on host capabilitiesGert Wollny2019-01-283-0/+13
| | | | | | | | | v2: - Use the renamed CAPS - add assetions to make sure that mesa doesn't try to switch destination surface formats when it is not supported. (Ilia Mirkin) Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* etnaviv: add linear sampling supportChristian Gmeiner2019-01-283-1/+25
| | | | | Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* etnaviv: update headers from rnndbChristian Gmeiner2019-01-288-55/+227
| | | | | | | Update to etna_viv commit 4d2f857. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* etnaviv: extend etna_resource with an addressing modeChristian Gmeiner2019-01-284-8/+22
| | | | | | | | | Defines how sampler (and pixel pipes) needs to access the data represented with a resource. The used default is mode is ETNA_ADDRESSING_MODE_TILED. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* nvc0: don't put text segment into bufctxIlia Mirkin2019-01-276-13/+16
| | | | | | | | | The text segment is shared among multiple contexts, while each one has its own bufctx. So when reallocating the text segment, some contexts may end up with stale values in their bufctx's. Instead limit the exposure to the bufctx to within a single draw. Signed-off-by: Ilia Mirkin <[email protected]>
* v3d: Create separate sampler states for the various blend formats.Eric Anholt2019-01-273-46/+299
| | | | | | | | | | | | The sampler border color is encoded in the TMU's blending format (half floats, 32-bit floats, or integers) and must be clamped to the format's range unorm/snorm/int ranges by the driver. Additionally, the TMU doesn't know about how we're abusing the swizzle to support BGRA, A, and LA, so we have to pre-swizzle the border color for those. We don't really want to spend half a kb on sampler states in most cases, so skip generating the variants when the border color is unused or is 0,0,0,0.
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