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* nvc0: enable RGB10_A2UI format on GK104Samuel Pitoiset2016-04-261-3/+3
| | | | | | | | | No clue why this was not enabled by default before, maybe because the SULDP conversion was wrong. Anyway, this helps in fixing all rgb10_a2ui piglit tests. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: shift address with blocksize for image buffersSamuel Pitoiset2016-04-261-0/+4
| | | | | | | This fixes a bunch of dEQP image buffers related tests. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: fix address offset when images have multiple levelsSamuel Pitoiset2016-04-261-0/+1
| | | | | | | This fixes arb_shader_image_load_store-level. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: bind images on 3D shaders for KeplerSamuel Pitoiset2016-04-262-2/+31
| | | | | | | Similar to surfaces validation for compute shaders. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: bind images on compute shaders for KeplerSamuel Pitoiset2016-04-264-28/+110
| | | | | | | | | | | Old surfaces validation code will be removed once images are completely done for Fermi/Kepler, that explains why I only disable it for now. This also introduces nvc0_get_surface_dims() which computes correct dimensions regarding the given target. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: reserve an area for surfaces info in the driver constbufSamuel Pitoiset2016-04-266-12/+12
| | | | | | | | | | | | | To process surfaces coordinates from the codegen part, and because some information like the format is not always available (eg. when writeonly is used), we have to stick some surfaces data in the driver constbuf. This is especially true for OpenCL because we don't know the format at shader compile time. This bumps the size of each shader area from 1K to 2K. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: add preliminary support for imagesSamuel Pitoiset2016-04-265-2/+74
| | | | | | | | | | | | This implements set_shader_images() and resource invalidation for images. As OpenGL requires at least 8 images, we are going to expose this minimum value even if this might be raised for Kepler, but this limit is mainly for Fermi because the hardware only accepts 8 images. Based on original patch by Ilia Mirkin. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gk110/ir: add emission for (a OP b) OP cSamuel Pitoiset2016-04-261-0/+26
| | | | | | | | This is pretty similar to NVC0 except that offsets have changed. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: "11.1 11.2" <[email protected]>
* nvc0/ir: fix wrong emission of (a OP b) OP cSamuel Pitoiset2016-04-261-2/+2
| | | | | | | | | | | The third source must be emitted at offset 49 instead of 17 and the not modifier is at 52 instead of 20. If you look a bit above in emitLogicOp() you will see that the dest is emitted at 17 which confirms that src(2) is obviously wrong. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: "11.1 11.2" <[email protected]>
* gallium: Include intrin.h instead of defining ourselves.Jose Fonseca2016-04-261-2/+1
| | | | | | | | | More portable, particularly when building with Clang, which implements all MSVC intrisincs in its own intrin.h, but doesn't actually support `#pragma instrinsic`. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* scons: Whenever possible decide what to do based on platform and not compiler.Jose Fonseca2016-04-261-4/+3
| | | | | | | | | | Because compilers like GCC and Clang are effectively available everywhere so their presence/absence is seldom conclusive. Furthermore, all compilers we use now have stdint.h. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radeonsi: Fix memory leak in error path.Bas Nieuwenhuizen2016-04-261-0/+2
| | | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix build error because of missing paramOded Gabbay2016-04-261-1/+1
| | | | | Signed-off-by: Oded Gabbay <[email protected]> Cc: "11.1 11.2" <[email protected]>
* r600g: use do_endian_swap in texture swapping functionOded Gabbay2016-04-261-1/+34
| | | | | | | | | For some texture formats we need to take "do_endian_swap" into account when configuring their swizzling. Signed-off-by: Oded Gabbay <[email protected]> Cc: "11.1 11.2" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: use do_endian_swap in color swapping functionsOded Gabbay2016-04-262-8/+14
| | | | | | | | | For some formats we need to take "do_endian_swap" into account when configuring swapping for color buffers. Signed-off-by: Oded Gabbay <[email protected]> Cc: "11.1 11.2" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: set endianess of 16/32-bit buffers according to do_endian_swapOded Gabbay2016-04-261-4/+13
| | | | | | | | | | | | | | | | | | This patch modifies r600_colorformat_endian_swap(), so for 16-bit and for 32-bit buffers, the endianess configuration will be determined not only by the color/texture format, but also by the do_endian_swap parameter. The only exception is for array formats, which are always set to not do swapping, because for them gallium sets an alias based on the machine's endianess. v4: V_0280A0_COLOR_16_16 and V_0280A0_COLOR_16_16_FLOAT should be set to 8IN16 because the bytes inside need to be swapped even for array formats. Signed-off-by: Oded Gabbay <[email protected]> Cc: "11.1 11.2" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g/radeonsi: send endian info to format translation functionsOded Gabbay2016-04-267-32/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because r600 GPUs can't do swap in their DB unit, we need to disable endianess swapping for textures that are handled by DB. There are four format translation functions in r600g driver: - r600_translate_texformat - r600_colorformat_endian_swap - r600_translate_colorformat - r600_translate_colorswap This patch adds a new parameters to those functions, called "do_endian_swap". When running in a big-endian machine, the calling functions will check whether the texture/color is handled by DB - "rtex->is_depth && !rtex->is_flushing_texture" - and if so, they will send FALSE through this parameter. Otherwise, they will send TRUE. The translation functions, in specific cases, will look at this parameter and configure the swapping accordingly. v4: evergreen_init_color_surface_rat() is only used by compute and don't handle DB surfaces, so just sent hard-coded FALSE to translation functions when called by it. Signed-off-by: Oded Gabbay <[email protected]> Cc: "11.1 11.2" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* tgsi: pass a shader type to the machine create and clean up.Dave Airlie2016-04-261-1/+1
| | | | | | | | | | | | | There was definitely bugs here mixing up the PIPE_ and TGSI_ defines, hopefully they didn't cause any problems, since mostly it was special cases for GEOMETRY. This clarifies at shader machine create what type of shader this machine will execute. This is needed also for compute shaders where we don't want to allocate inputs/outputs. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: fix missing include for Elements.Dave Airlie2016-04-261-0/+1
| | | | | | Since u_blitter.h no longer defines this. Signed-off-by: Dave Airlie <[email protected]>
* nvc0: bump the amount of shared memory per MP on MaxwellSamuel Pitoiset2016-04-261-1/+11
| | | | | | | | According to the CUDA compute capability version, GM10x can expose 64KB of shared memory while GM20x can use 96KB. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* r600: fix missing include for Elements macroDave Airlie2016-04-261-0/+1
| | | | | | | This got removed from u_blitter.h and we were taking it from there, this should just move to ARRAY_SIZE eventually. Signed-off-by: Dave Airlie <[email protected]>
* gm107/ir: s/invalid load/invalid store/Samuel Pitoiset2016-04-251-1/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: remove unused fxnRob Clark2016-04-251-6/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: convert over to rallocRob Clark2016-04-252-40/+6
| | | | | | | | | The home-grown heap scheme (which is ultra-simple but probably not good to always allocate and memset such a chunk of memory up front) was a remnant of fdre (where the ir originally came from). But since we have ralloc in mesa, lets just use that instead. Signed-off-by: Rob Clark <[email protected]>
* freedreno: honor handle->offsetRob Clark2016-04-251-2/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: disallow cat4 immed srcRob Clark2016-04-251-1/+1
| | | | | | | | Normally this would never happen (constant-propagation in NIR would eliminate the instruction), except it does happen for 'undef' which we turn into immed 0.0 for bookkeeping purposes. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: add render-target formatsRob Clark2016-04-251-3/+3
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2016-04-255-5/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: reduce line width for deqp furtherRob Clark2016-04-251-1/+1
| | | | | | | | See a7eb12d0.. but that wasn't restrictive enough. Fixes dEQP-GLES3.functional.rasterization.primitives.line_strip_wide, and similar Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix sin/cosRob Clark2016-04-258-1/+92
| | | | | | | | | | We seem to need range reduction to get sane results. Fixes glmark2 jellyfish bench, and a whole bunch of dEQP-GLES3.functional.shaders.builtin_functions.precision.{sin,cos,tan}.* v2: squashed in android build fixes from Rob Herring Signed-off-by: Rob Clark <[email protected]>
* svga: eliminiate unnecessary constant buffer updatesCharmaine Lee2016-04-253-2/+23
| | | | | | | | | | | | | | | | | | Currently if the texture binding is changed, emit_fs_consts() is triggered to update texture scaling factor for rectangle texture or texture buffer size in the constant buffer. But the update is only relevant if the texture binding includes a rectangle texture or a texture buffer. To eliminate the unnecessary constant buffer updates due to other texture binding changes, a new flag SVGA_NEW_TEXTURE_CONSTS will be used to trigger fragment shader constant buffer update when a rectangle texture or a texture buffer is bound. With this patch, the number of constant buffer updates in Lightsmark2008 reduces from hundreds per frame to about 28 per frame. Reviewed-by: Brian Paul <[email protected]>
* svga: mark the texture dirty for write transfer map onlyCharmaine Lee2016-04-251-2/+4
| | | | | | | | | Instead of unconditionally mark the texture subresource dirty at transfer map, we'll set the dirty bit for write transfer only. Tested with lightsmark2008 and glretrace. Reviewed-by: Brian Paul <[email protected]>
* svga: fix assert with PIPE_QUERY_OCCLUSION_PREDICATE for non-vgpu10Charmaine Lee2016-04-251-23/+20
| | | | | | | | | | With this patch, when running in hardware version 11, we'll use SVGA3D_QUERYTYPE_OCCLUSION query type for PIPE_QUERY_OCCLUSION_PREDICATE and return TRUE if samples-passed count is greater than 0. Fixes glretrace/solidworks2012_viewport running in hardware version 11. Reviewed-by: Brian Paul <[email protected]>
* svga: minimize surface flushCharmaine Lee2016-04-252-15/+85
| | | | | | | | | | | | Currently, we always do a surface flush when we try to establish a synchronized write transfer map. But if the subresource has not been modified, we can skip the surface flush. In other words, we only need to do a surface flush if the to-be-mapped subresource has been modified in this command buffer. With this patch, lightsmark2008 shows about 15% performance improvement. Reviewed-by: Brian Paul <[email protected]>
* svga: s/Elements/ARRAY_SIZE/Brian Paul2016-04-2519-55/+55
| | | | | | Standardize on the later macro rather than a mix of both. Reviewed-by: Charmaine Lee <[email protected]>
* svga: whitespace and formatting fixes in svga_pipe_rasterizer.cBrian Paul2016-04-251-16/+13
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* svga: whitespace and formatting fixes in svga_pipe_depthstencil.cBrian Paul2016-04-251-14/+14
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* svga: whitespace and formatting fixes in svga_pipe_sampler.cBrian Paul2016-04-251-31/+33
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* svga: separate HUD counters for state objectsBrian Paul2016-04-257-12/+29
| | | | | | | | | | Count depth/stencil, blend, sampler, etc. state objects separately but just report the sum for the HUD. This change lets us use gdb to see the breakdown of state objects in more detail. Also, count sampler views too. Reviewed-by: Charmaine Lee <[email protected]>
* gallium: fix warnings in release buildGrazvydas Ignotas2016-04-255-5/+6
| | | | | | | | Mark variables MAYBE_UNUSED to avoid unused-but-set-variable warnings in release build. Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* nouveau: codegen: combineLd/St do not combine indirect loadsHans de Goede2016-04-251-0/+7
| | | | | | | | | | | | | | | | | | | | | combineLd/St would combine, i.e. : st u32 # g[$r2+0x0] $r2 st u32 # g[$r2+0x4] $r3 into: st u64 # g[$r2+0x0] $r2d But this is only valid if r2 contains an 8 byte aligned address, which is not guaranteed for compute shaders This commit checks for src0 dim 0 not being indirect when combining loads / stores as combining indirect loads / stores may break alignment rules. Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: relax restriction in groupingRob Clark2016-04-241-3/+5
| | | | | | | | | | Currently we were two restrictive, and would insert an output move in cases like: MOV OUT[0], IN[0].xyzw Loosen the restriction to allow the current instruction to appear in the neighbor list but only at it's current possition. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix small memory leakRob Clark2016-04-241-0/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix small RA bugRob Clark2016-04-241-1/+2
| | | | | | | Normally the offset in the group would be the same, but not always. For example, in a sam(w) which only writes the 4th component. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: better workaround for astc+srgbRob Clark2016-04-2410-22/+195
| | | | | | | | | | | | | | | This *seems* like a hw bug, and maybe only applies to certain a4xx variants/revisions. But setting the SRGB bit in sampler view state (texconst0) causes invalid alpha for ASTC textures. Work around this setting up a second texture state and using that to sample alpha separately. This way, srgb->linear conversion happens in hw *prior* to interpolation. This fixes 546 dEQP tests: dEQP-GLES3.functional.texture.*astc*srgb* Signed-off-by: Rob Clark <[email protected]>
* Revert "freedreno/a4xx: lower srgb in shader for astc textures"Rob Clark2016-04-247-62/+6
| | | | | | Better workaround in the following patch. This reverts commit 899bd63acefd49a668e11c42d2ad92fa55aa157d.
* freedreno/a4xx: blend state no longer depends on fb stateRob Clark2016-04-241-4/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeonsi: Implement ddx/ddy on VI using ds_bpermuteTom Stellard2016-04-221-12/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | The ds_bpermute instruction allows threads to transfer data directly to or from the vgprs of other threads. These instructions use the LDS hardware to transfer data, but do not read or write LDS memory. DDX BEFORE: | DDX AFTER: | v_mbcnt_lo_u32_b32_e64 v2, -1, 0 | v_mbcnt_lo_u32_b32_e64 v2, -1, 0 v_mbcnt_hi_u32_b32_e64 v2, -1, v2 | v_mbcnt_hi_u32_b32_e64 v2, -1, v2 v_lshlrev_b32_e32 v4, 2, v2 | v_and_b32_e32 v2, 60, v2 v_and_b32_e32 v2, 60, v2 | v_lshlrev_b32_e32 v2, 2, v2 v_lshlrev_b32_e32 v3, 2, v2 | ds_bpermute_b32 v3, v2, v0 s_mov_b32 m0, -1 | ds_bpermute_b32 v0, v2, v0 offset:4 ds_write_b32 v4, v0 | s_waitcnt lgkmcnt(0) s_waitcnt lgkmcnt(0) | v_or_b32_e32 v0, 1, v2 | v_lshlrev_b32_e32 v0, 2, v0 | ds_read_b32 v1, v3 | ds_read_b32 v0, v0 | s_waitcnt lgkmcnt(0) | | LDS: 1 blocks | LDS: 0 blocks Reviewed-by: Michel Dänzer <[email protected]> Acked-by: Marek Olšák <[email protected]>
* radeonsi: Use llvm.amdgcn.mbcnt.* intrinsics instead of llvm.SI.tidTom Stellard2016-04-221-1/+16
| | | | | | | | | | | We're trying to move to more of the new style intrinsics with include the correct target name, and map directly to ISA instructions. v2: - Only do this with LLVM 3.8 and newer. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Set range metadata on calls to llvm.SI.tidTom Stellard2016-04-221-3/+26
| | | | | | | | The range metadata tells LLVM the range of expected values for this intrinsic, so it can do some additional optimizations on the result. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
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