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* freedreno: add robustness supportRob Clark2019-04-254-0/+57
| | | | Signed-off-by: Rob Clark <[email protected]>
* panfrost/midgard: Add new bitwise opsAlyssa Rosenzweig2019-04-252-6/+24
| | | | | | These fused NOT-ops could maybe help somehow...? Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Identify inandAlyssa Rosenzweig2019-04-253-3/+7
| | | | | | | This was previously thought to be inot, but it's actually a bit more general than that! :) Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Copy prop for texture registersAlyssa Rosenzweig2019-04-251-2/+35
| | | | | | | | We'll want to unify this with main copy prop (and extend to varyings), but that'll take more care to handle some special cases, so leave it as a stub pass for now. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Optimize csel involving 0Alyssa Rosenzweig2019-04-252-15/+30
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Extend copy propagation passAlyssa Rosenzweig2019-04-251-8/+48
| | | | | | | | This extends copy propagation to respect output modifiers for ALU instructions, as well as potentially fixing some bugs related to looping (all dEQP loop tests pass). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Reduce fmax(a, 0.0) to fmov.posAlyssa Rosenzweig2019-04-251-3/+33
| | | | | | | This will allow us to copyprop away the move and eliminate the instruction entirely. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* ac/nir: Add support for planes.Bas Nieuwenhuizen2019-04-251-0/+7
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* iris: make the TFB result visible to othersAndrii Simiklit2019-04-251-10/+15
| | | | | | | | | | | | | | | | | | | | | | OpenGL 4.6 Spec: "5.3.3 Rules ....... Note: “Updates” via rendering or transform feedback are treated consistently with updates via GL commands. Once EndTransformFeedback has been issued, any subsequent command in the same context that uses the results of the transform feedback operation will see the results." v2: removed a wrong comment ( Kenneth Graunke <[email protected]> ) v3: - flush+dirty depends on buffers usage history - removed an old hack ( Kenneth Graunke <[email protected]> ) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110404 Signed-off-by: Andrii Simiklit <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Some tidying for preemption supportKenneth Graunke2019-04-254-98/+102
| | | | | | | | Just enable it during init_render_context on Gen10+, and move the Gen9 state tracking into iris_genx_state so it only exists on Gen9. Reviewed-by: Mike Blumenkrantz <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* radeonsi: remove dirty slot masks from scissor and viewport statesMarek Olšák2019-04-256-93/+40
| | | | | | All registers in the array need to be updated if any of them is changed. Only apps writing gl_ViewportIndex were affected by this bug.
* radeonsi/gfx9: rework the gfx9 scissor bug workaround (v2)Marek Olšák2019-04-258-48/+68
| | | | | | | | | | | Needed to track context rolls caused by streamout and ACQUIRE_MEM. ACQUIRE_MEM can occur outside of draw calls. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110355 v2: squashed patches and done more rework Cc: 19.0 <[email protected]>
* radeonsi/gfx9: set that window_rectangles always roll the contextMarek Olšák2019-04-251-1/+2
| | | | Cc: 19.0 <[email protected]>
* radeonsi: add radeonsi_sync_compile optionNicolai Hähnle2019-04-252-3/+11
| | | | | | | | | Force the driver thread to sync immediately with a compiler thread (but compilation still happens in a separate thread). This can be useful to simplify debugging compiler issues. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add radeonsi_aux_debug option for aux context debug dumpsNicolai Hähnle2019-04-253-1/+33
| | | | | | | | Enabling this option will create ddebug-style dumps for the aux context, except that instead of intercepting the pipe_context layer we just dump the IB contents on flush. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add si_debug_options for convenient adding/removing of optionsNicolai Hähnle2019-04-256-16/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the definition of radeonsi_clear_db_cache_before_clear there, as well as radeonsi_enable_nir. This removes the AMD_DEBUG=nir option. We currently still have two places for options: the driconf machinery and AMD_DEBUG/R600_DEBUG. If we are to have a single place for options, then the driconf machinery should be preferred since it's more flexible. The only downside of the driconf machinery was that adding new options was quite inconvenient. With this change, a simple boolean option can be added with a single line of code, same as for AMD_DEBUG. One technical limitation of this particular implementation is that while almost all driconf features are available, the translation machinery doesn't pick up the description strings for options added in si_debvug_options. In practice, translations haven't been provided anyway, and this is intended for developer options, so I'm not too worried. It could always be added later if anybody really cares. v2: - use bool instead of uint8_t for options - si_debug_options.inc -> si_debug_options.h Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add BOs after need_cs_spaceMarek Olšák2019-04-242-6/+6
| | | | | | | | need_cs_space may clear the buffer list. Fixes: 951d60f8cdc88 "radeonsi: delay adding BOs at the beginning of IBs until the first draw" Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* v3d: Disable SSBOs and atomic counters on vertex shaders.Eric Anholt2019-04-241-0/+3
| | | | | | | | | | The CTS fails on dEQP-GLES31.functional.shaders.opaque_type_indexing.atomic_counter.*vertex when they are enabled, due to the VS being run for both bin and render. I think this behavior is expected to be valid, but I can't find text in atomic counters or SSBO specs saying so (the closed I found was in shader_image_load_store). Just disable it for now, since the closed source driver doesn't expose vertex atomic counters/SSBOs either.
* iris: Advertise EXT_texture_sRGB_R8 supportKenneth Graunke2019-04-241-0/+1
| | | | Using the luminance format, like both brw and anv do.
* iris: Enable GL_AMD_depth_clamp_separateKenneth Graunke2019-04-241-0/+1
| | | | We support this, we just forgot to turn it on.
* iris: enable preemption support for gen10Mike Blumenkrantz2019-04-241-0/+2
| | | | | | | | this automatically enables preemption on gen10 where it is disabled by default but still available Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* iris: add preemption support on gen9Mike Blumenkrantz2019-04-243-0/+99
| | | | | | | | | | | this is basically just porting the following two commits to gallium: d8b50e152a0d5df0971c05b8db132fa688794001 5c454661c66fa2624cf4bba1071175070724869a resolves kwg/mesa#49 Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* iris: Split iris_flush_and_dirty_for_history into two helpers.Kenneth Graunke2019-04-242-20/+46
| | | | | | | | | | | | | | We create two new helpers, iris_flush_bits_for_history, and iris_dirty_for_history, then use them in the existing function. The first accumulates flush bits based on res->bind_history, but doesn't actually perform a flush. This allows us to accumulate flush bits by looping over multiple resources, but ultimately emit a single flush for all of them. The latter flags dirty bits without flushing, which again allows us to handle multiple resources, but also is more convenient when writing from the CPU where we don't need a flush (as in commit 4d12236072).
* iris: Actually put Mesa in GL_RENDERER stringKenneth Graunke2019-04-241-1/+1
| | | | I constructed the right thing and then returned the other one.
* gallium: add PIPE_CAP_PREFER_COMPUTE_BLIT_FOR_MULTIMEDIAMarek Olšák2019-04-241-0/+1
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* gallium: set PIPE_CAP_MAX_FRAMES_IN_FLIGHT to 2 for all driversMarek Olšák2019-04-249-26/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* android/iris: fix driinfo header filenameTapani Pälli2019-04-231-1/+1
| | | | | | | | Fixes iris driver Android build. Fixes: faa52e328e3 "iris: Add mechanism for iris-specific driconf options" Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* panfrost/midgard: Remove assemblerAlyssa Rosenzweig2019-04-241-643/+0
| | | | | | | This code is outdated and unused; now that the compiler is mature, there's no point keeping it around in-tree (or at all). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Adds Bifrost shader disassembler utilityRyan Houdek2019-04-245-0/+2434
| | | | | | | | | | | | | This code is stable and can live upstream independently while the rest of the Bifrost stack comes up. v2: Added a verbose flag to hide away some of the more verbose features that nobody really needs [The Bifrost disassembler is written by Connor Abbott, Lyude Paul, and Ryan Houdek.] Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Add "op commutes?" propertyAlyssa Rosenzweig2019-04-242-49/+36
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Refactor opcode tablesAlyssa Rosenzweig2019-04-244-227/+124
| | | | | | | | | | | We create an all-encompassing opcode table for handling name and properties, removing a number of ad hoc opcode tables which became brittle and quickly out of date. While we're at it, we fix some incorrect opcodes relating to ball/bany, and move a small function out to midgard_compile.c. Together these changes should allow compilation without warnings, along with helping the codebase health considerably. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Optimize MIR in progress loopAlyssa Rosenzweig2019-04-241-5/+11
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Implement copy propagationAlyssa Rosenzweig2019-04-242-1/+78
| | | | | | | | | Most copy prop should occur at the NIR level, but we generate a fair number of moves implicitly ourselves, etc... long story short, it's a net win to also do simple copy prop + DCE on the MIR. As a bonus, this fixes the weird imov precision bug once and for good, I think. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Set integer modsAlyssa Rosenzweig2019-04-241-10/+28
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Document sign-extension/zero-extension bits (vector)Alyssa Rosenzweig2019-04-243-18/+57
| | | | | | | | For floating point ops, these bits determine the "negate?" and "abs?" modifiers. For integer ops, it turns out they control how sign/zero extension work, useful for mixing types. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Update integer op listAlyssa Rosenzweig2019-04-241-10/+21
| | | | | | | In the future, we might want to switch to a table-based approach, but for now, at least have it current. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Remove unused mir_next_blockAlyssa Rosenzweig2019-04-241-7/+0
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Fix off-by-one in successor analysisAlyssa Rosenzweig2019-04-241-2/+4
| | | | | | | This reduces register pressure substantially since we get smaller liveness ranges. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Track loop depthAlyssa Rosenzweig2019-04-241-7/+10
| | | | | | This fixes nested loops. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Dead code eliminate MIRAlyssa Rosenzweig2019-04-241-15/+10
| | | | | | | | We reshuffle the existing "dead move elimination" pass into a generic dead code elimination layer, fixing bugs incurred with looping in the process. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use actual imov instructionAlyssa Rosenzweig2019-04-241-1/+1
| | | | | | | The bug this worked around is no longer applicable, it seems -- remove the hack that breaks more than it fixes. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Disable indirect outputs for nowAlyssa Rosenzweig2019-04-242-3/+8
| | | | | | | The hardware needs this lowered anyway; for now, might as well use mesa's default lowering for pure conformance reasons. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: imul can only run on *mulAlyssa Rosenzweig2019-04-241-1/+1
| | | | | | | | This restriction makes sense logically. Not sure why it wasn't obeyed before. In conjunction with previous commit's disclaimer, fixes dEQP-GLES2.functional.shaders.loop.for_dynamic_iterations.* Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Don't try to inline constants on branchesAlyssa Rosenzweig2019-04-241-0/+3
| | | | | | | | Along with a corresponding fix to the move elimination pass (not included here yet -- I just have it disabled for now), this will fix dEQP-GLES2.functional.shaders.loops.for_uniform_iterations.* Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Respect backwards branches in RAAlyssa Rosenzweig2019-04-241-14/+69
| | | | | | | Fixes a bunch of issues with looping. Honestly, I'm not sure why loops worked at all before. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Remove useless MIR dumpAlyssa Rosenzweig2019-04-241-2/+0
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Respect component of bcsel conditionAlyssa Rosenzweig2019-04-241-7/+22
| | | | | | Fixes a bunch of non-vec4 indexing.varying_array tests. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Implement indirect loads of varyings/UBOsAlyssa Rosenzweig2019-04-242-16/+76
| | | | | | | | This adds preliminary support for indirect loads of varying arrays and uniform arrays, bringing a few new tests in shader.indexing.* to passing, although there remains a number of cases still missing. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Pipe through varying arraysAlyssa Rosenzweig2019-04-241-1/+5
| | | | | | | | Varying arrays sometimes are lowered to a series of directly accessed varyings (which we handled okay), but when indirectly accessed, they appear as a single array; we need to handle this as well. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/mdg/disasm: Print raw varying_parametersAlyssa Rosenzweig2019-04-241-1/+1
| | | | | | | | | | The semantics of this field are not well understood; it is better to print it unconditionally along with the other unknown state, rather than silently eat the value. Without this change, some critical state was being lost in some shaders (notably, the offset for load/store scratchpad intructions found in shaders that spill registers.) Signed-off-by: Alyssa Rosenzweig <[email protected]>
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