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* scons/svga: remove opt from the list of valid build typesBrian Paul2018-10-261-2/+0
| | | | | | | | | This reverts commit a5fd54f8bf6713312fa5efd7ef5cd125557a0ffe. The whole point was to add a way to pass -DVMX86_STATS to the build, but we can do that with a command line argument when we invoke scons. Reviewed-by: José Fonseca <[email protected]>
* radeon/vcn: use util function to get h264 profile idcBoyuan Zhang2018-10-261-2/+1
| | | | | | | | Use utility function for converting h264 pipe video profile to profile idc, instead of using array. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <christian.koenig at amd.com>
* radeon/vce: use util function to get h264 profile idcBoyuan Zhang2018-10-262-8/+2
| | | | | | | | Use utility function for converting h264 pipe video profile to profile idc, instead of using array. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <christian.koenig at amd.com>
* util: Change remaining uint32 cache ids to sha1David McFarland2018-10-263-67/+69
| | | | | | | | | | | | After discussion with Timothy Arceri. disk_cache_get_function_identifier was using only the first byte of the sha1 build-id. Replace disk_cache_get_function_identifier with implementation from radv_get_build_id. Instead of writing a uint32_t it now writes to a mesa_sha1. All drivers using disk_cache_get_function_identifier are updated accordingly. Reviewed-by: Timothy Arceri <[email protected]> Fixes: 83ea8dd99bb1 ("util: add disk_cache_get_function_identifier()")
* freedreno: use fd_bc_alloc_batch instead of fd_batch_create.Hyunjun Ko2018-10-252-2/+2
| | | | | | | | | | Following the commit 2385d7b066 and 8e798e28f7, for resource dependancy tracking. Fixes: dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_depth_fbo with FD_MESA_DEBUG=inorder Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: take reg->num out of union in ir3_registerHyunjun Ko2018-10-251-5/+6
| | | | | | | | | | To avoid wrong result when identifying the type of register. Ie. If the reg is an array, it might be identified as address or predicate register. Fixes: dEQP-GLES31.functional.ssbo.layout.random.arrays_of_arrays.6 Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: disable unused groupsRob Clark2018-10-252-6/+13
| | | | | | | | Don't leave vsconst/fsconst group enabled if we switch to shader with no uniforms. Fixes: abcdf5627a2 freedreno/a6xx: move const emit to state group Signed-off-by: Rob Clark <[email protected]>
* freedreno: add useful assertRob Clark2018-10-251-1/+3
| | | | | | | Would have been useful to catch the problem fixed in 8e798e28f736e22e9e1e4534ab42a36cde14b142 Signed-off-by: Rob Clark <[email protected]>
* swr/rast: ignore CreateElementUnorderedAtomicMemCpyAlok Hota2018-10-251-1/+2
| | | | | | | | | This function's API changed between LLVM 5 and 6. Compile errors occur when building with LLVM 6+ if LLVM 5 was used for a dist tarball CC: <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107865 Reviewed-by: Emil Velikov <[email protected]>
* swr/rast: fix intrinsic/function for LLVM 7 compatibilityAlok Hota2018-10-256-14/+3
| | | | | | | | | | | | Converted from x86 VFMADDPS intrinsic to generic LLVM intrinsic, and removed createInstructionSimplifierPass, which were both removed in LLVM 7.0.0 These changes combine patches we received from the community and our own internal patches Reviewed-by: Bruce Cherniak <[email protected]> Tested-by: Chuck Atkins <[email protected]>
* nvc0: increase NOUVEAU_TRANSFER_PUSHBUF_THRESHOLD to 1024 on Kepler+Rhys Perry2018-10-254-3/+11
| | | | | | | | Gives a +3.89% to +5.27% FPS improvement with Hitman and +2.73% to +2.82% FPS improvement with Dirt Rally on my GTX 1060. Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* util: use C99 declaration in the for-loop set_foreach() macroEric Engestrom2018-10-254-6/+0
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* util: use C99 declaration in the for-loop hash_table_foreach() macroEric Engestrom2018-10-2510-20/+0
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* ir3_compiler/nir: fix imageSize() for buffer-backed imagesEduardo Lima Mitev2018-10-242-0/+33
| | | | | | | | | | | | | | | | | | | | | | GL_EXT_texture_buffer introduced texture buffers, which can be used in shaders through a new type imageBuffer. Because how image access is implemented in freedreno, calling imageSize on an imageBuffer returns the size in bytes instead of texels, which is incorrect. This patch adds a division of imageSize result by the bytes-per-pixel of the image format, when image is buffer-backed. Fixes all tests under dEQP-GLES31.functional.image_load_store.buffer.image_size.* v2: Pre-compute and submit the log2 of the image format's bpp as shader constant instead of emitting the LOG2 instruction in code. (Rob Clark) v3: Use ffs (find-first-bit) helper for computing log2 (Ilia Mirkin) Reviewed-by: Rob Clark <[email protected]>
* radeonsi: enable vcn jpeg decode for ravenBoyuan Zhang2018-10-231-0/+2
| | | | | | | Enable vcn jpeg decode for raven. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: implement jpeg target buffer cmdBoyuan Zhang2018-10-231-1/+72
| | | | | | | | Implement jpeg target buffer cmd by programming registers directly, since there is no firmware for VCN Jpeg decode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Leo Liu <[email protected]>
* radeon/vcn: implement jpeg bitstream buffer cmdBoyuan Zhang2018-10-231-1/+45
| | | | | | | | Implement jpeg bitstream buffer cmd by programming registers directly, since there is no firmware for VCN Jpeg decode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Leo Liu <[email protected]>
* radeon/uvd: remove get mjpeg slice headerBoyuan Zhang2018-10-231-157/+0
| | | | | | | | Move the previous get_mjpeg_slice_heaeder function and eoi from "radeon/vcn" to "st/va". Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: add jpeg decode implementationBoyuan Zhang2018-10-235-7/+119
| | | | | | | | Add a new file to handle VCN Jpeg decode specific functions. Use Jpeg specific cmd sending function in end_frame call. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: separate send cmd call from end frameBoyuan Zhang2018-10-232-8/+28
| | | | | | | | Use function pointer for sending cmd in end_frame call. By doing this, we can assign different cmd sending logics for Jpeg decode later. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: create cs based on ring typeBoyuan Zhang2018-10-231-2/+6
| | | | | | | Add RING_VCN_JPEG for VCN Jpeg decode, and keep RING_VCN_DEC for other codecs. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/winsys: add vcn jpeg ring typeBoyuan Zhang2018-10-231-0/+1
| | | | | | | Add a new ring type for vcn jpeg. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: add vcn jpeg decode interfaceBoyuan Zhang2018-10-231-0/+90
| | | | | | | Add VCN Jpeg decode interfaces and register defines. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: move radeon decoder define to header fileBoyuan Zhang2018-10-232-31/+32
| | | | | | | | Move radeon_decoder definition from "radeon_vcn_dec.c" to "radeon_vcn_dec.h", so that it can be included by other files later. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* android: Build kms_swrast for the Android platformRob Herring2018-10-221-2/+2
| | | | | | Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Robert Foss <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* ir3/nir: Set up image_dims consts for image_deref_size intrinsic tooEduardo Lima Mitev2018-10-211-0/+1
| | | | | | | | | `nir_intrinsic_image_deref_size` is not being considered during scan for driver constants, so image constants are not emitted if a shader only ever query the size of an image (no load, store, atomic op, etc). This is unlikely, but possible. Reviewed-by: Rob Clark <[email protected]>
* nv50/ir: fix ConstantFolding::createMul for 64 bit mulsKarol Herbst2018-10-201-1/+1
| | | | | | | | Fixes: 2f52925f5c60c72c9389bfdc122c3d5f8e15b25f "nv50/ir: move a * b -> a << log2(b) code into createMul()" Reviewed-by: Rhys Perry <[email protected]> Signed-off-by: Karol Herbst <[email protected]>
* radeonsi: Disable clear_state with radeon kernel driverSonny Jiang2018-10-192-4/+7
| | | | | Signed-off-by: Sonny Jiang <[email protected]> Tested-by: Michel Dänzer <[email protected]>
* radeonsi: fix a typo in a comment in emit_guardbandMarek Olšák2018-10-181-1/+1
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* radeonsi: fix gnome-shell crashMarek Olšák2018-10-181-2/+2
| | | | | | | I wasn't expecting to get viewports with the center having negative coordinates. Broken by: 6cc79e4411f
* radeonsi: clamp point size to the limitMarek Olšák2018-10-183-3/+5
| | | | | | | This fixes dEQP-GLES2.functional.rasterization.limits.points. Broken by: ea039f789d9b54e1bd1d644b6a29863ca3500314 Tested-by: Jakob Bornecrantz <[email protected]>
* radeonsi: fix a VGT hang with primitive restart on Polaris10 and laterMarek Olšák2018-10-181-2/+8
| | | | | Cc: 18.1 18.2 <[email protected]> Tested-by: Jakob Bornecrantz <[email protected]>
* radeonsi: fix a deadlock due to partially-initialized context on CIMarek Olšák2018-10-181-6/+8
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* radeonsi: Bump number of allowed global buffers to 32Jan Vesely2018-10-181-1/+1
| | | | | | | | Fixes assertion failure/crash when running luxmark/luxball on clover. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108272 CC: [email protected] Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix incorrect hw screen offset and guardband computationMarek Olšák2018-10-181-2/+2
| | | | | | It resulted in assertion failures or incorrect rendering. Broken by: 9e182b8313c5ab952498a76495f57e8420f9e5ad
* Fix setting indent-tabs-mode in the Emacs .dir-locals.el filesNeil Roberts2018-10-173-3/+3
| | | | | | | Some of the .dir-locals.el had the wrong name for the truthy value so it wasn’t setting indent-tabs-mode. Reviewed-by: Ilia Mirkin <[email protected]>
* freedreno/a6xx: don't allocate binning rbRob Clark2018-10-171-3/+7
| | | | | | | Now that a single cmdstream is used for both binning and draw passes, we can skip allocation of cmdstream buffer for binning. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: single cmdstream for draw+binningRob Clark2018-10-173-15/+3
| | | | | | | | | | | Now that state which is different for draw vs binning pass is split out into different state-groups with appropriate enable_mask (so the appropriate one is chosen for draw vs binning), switch over to using a single cmdstream for both passes. This should significantly lower draw overhead for CPU bound benchmarks. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: split binning vs draw program stateobj'sRob Clark2018-10-172-4/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: split VBO state into binning/draw variantsRob Clark2018-10-172-1/+8
| | | | | | | | Blob seems to manage to use same input registers for BS (binning pass) vs VS (draw pass) shaders, so it can use the same VBO state for both. We can't quite do that yet, so split them. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: move VBO state to stateobjRob Clark2018-10-173-8/+19
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: move ZSA state to stateobjRob Clark2018-10-172-19/+39
| | | | | | | Step towards single cmdstream, where we need different state-group-id's for binning vs draw ZSA state. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: remove vismode paramRob Clark2018-10-171-14/+2
| | | | | | | We don't need to keep this IGNORE_VISIBILITY in binning pass. Prep work for using single cmdstream for both draw and binning passes. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move binning-pass fixup for a6xx+Rob Clark2018-10-171-20/+37
| | | | | | | | | Move this to after ir3_cp (which can add lowered immediates to the const state) for a6xx+, to ensure the uniform state matches between binning and vertex shaders. This way we can emit just a single VS_CONST state- group when we re-use single cmdstream for both binning and draw passes. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: a bit more state emit cleanupRob Clark2018-10-174-37/+27
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: move framebuffer state emit to emit_mrt()Rob Clark2018-10-172-29/+24
| | | | | | | No point in checking this per-draw, since framebuffer change means new batch. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: small emit_mrt() cleanupRob Clark2018-10-171-14/+7
| | | | | | | On a6xx, this is only used for pfb->cbufs so we can just directly pass the pfb state. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: use program cacheRob Clark2018-10-177-130/+247
| | | | | | | Use the in-memory cache to construct shader program state and re-use it on subsequent draws, to lower driver overhead. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: shader variant cacheRob Clark2018-10-175-0/+214
| | | | | | | | | | Cache that maps gallium hwcso (in this case, 'struct ir3_shader') plus shader variant key to a generation specific state object. This could eventually replace the linked list of shader variants, but for now it lets us re-use the work currently done in fdN_program_emit() Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move binning_pass out of shader variant keyRob Clark2018-10-1721-75/+109
| | | | | | | | | | | Prep work for a following patch, that introduces a cache to map from program state (all shader stages) plus variant key to pre-baked hw state (which could be emit'd via CP_SET_DRAW_STATE, for example). To do that, we really want the variant key to be immutable, and to treat the binning pass shader as an extra shader stage, rather than as a VS variant. Signed-off-by: Rob Clark <[email protected]>
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