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* freedreno/ir3: use pipe_debug_callback for shader-db tracesRob Clark2016-04-306-33/+43
| | | | | | For multi-threaded shader-db support. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: add debug callback to emitRob Clark2016-04-303-0/+6
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: add debug callback to emitRob Clark2016-04-303-0/+7
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: wire up core pipe_debug_callbackRob Clark2016-04-302-0/+15
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle color clamp variant ourselvesRob Clark2016-04-305-3/+28
| | | | | | | | | Now that there is a pass to do this in NIR, lets just use that and manage the variants ourself, rather than letting state-tracker do it. This way, mesa/st will precompile shaders without requiring ST_DEBUG=precompile (which requires a debug build). Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix indentationRob Clark2016-04-303-12/+12
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeonsi: fix synchronization of shader imagesMarek Olšák2016-04-301-7/+11
| | | | | | | This fixes the winsys->cs_is_buffer_referenced query, which is used for synchronization before buffers are mapped. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: fix crash in r600_set_streamout_targetsNicolai Hähnle2016-04-292-7/+9
| | | | | | | | Protect against dereferencing a gap in the targets array. This was triggered by a test in the Khronos CTS. Cc: "11.1 11.2" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nir: Switch the arguments to nir_foreach_use and friendsJason Ekstrand2016-04-281-1/+1
| | | | | | | | | | | This matches the "foreach x in container" pattern found in many other programming languages. Generated by the following regular expression: s/nir_foreach_use(\([^,]*\),\s*\([^,]*\))/nir_foreach_use(\2, \1)/ and similar expressions for nir_foreach_use_safe, etc. Reviewed-by: Ian Romanick <[email protected]>
* nir: Switch the arguments to nir_foreach_functionJason Ekstrand2016-04-286-7/+7
| | | | | | | | | This matches the "foreach x in container" pattern found in many other programming languages. Generated by the following regular expression: s/nir_foreach_function(\([^,]*\),\s*\([^,]*\))/nir_foreach_function(\2, \1)/ Reviewed-by: Ian Romanick <[email protected]>
* nir: Switch the arguments to nir_foreach_phi_srcJason Ekstrand2016-04-281-1/+1
| | | | | | | | | | | This matches the "foreach x in container" pattern found in many other programming languages. Generated by the following regular expression: s/nir_foreach_phi_src(\([^,]*\),\s*\([^,]*\))/nir_foreach_phi_src(\2, \1)/ and a similar expression for nir_foreach_phi_src_safe. Reviewed-by: Eduardo Lima Mitev <[email protected]>
* nir: Switch the arguments to nir_foreach_instrJason Ekstrand2016-04-286-9/+9
| | | | | | | | | | | This matches the "foreach x in container" pattern found in many other programming languages. Generated by the following regular expression: s/nir_foreach_instr(\([^,]*\),\s*\([^,]*\))/nir_foreach_instr(\2, \1)/ and similar expressions for nir_foreach_instr_safe etc. Reviewed-by: Ian Romanick <[email protected]>
* nvc0: stick compute kernel arguments into uniform_boSamuel Pitoiset2016-04-295-26/+10
| | | | | | | | | | | | | Having one buffer object for input kernel arguments coming from clover and an other one for OpenGL user uniforms is unnecessary. Using the uniform_bo object for both GL/CL uniforms avoids to declare a new BO. This only affects compute programs but it should not hurt anything because the states are dirtied and data will get reuploaded. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Hans de Goede <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* swr: remove duplicated constant update codeTim Rowley2016-04-281-44/+47
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* gallium/radeon: add the size only once in r600_context_add_resource_sizeMarek Olšák2016-04-281-5/+3
| | | | Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: drop support for LINEAR_GENERAL layoutMarek Olšák2016-04-286-85/+20
| | | | | | | Unused. All texture imports use LINEAR_ALIGNED regardless of what the DDX does. Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: rework clear_buffer flagsMarek Olšák2016-04-289-32/+46
| | | | | | | | | Changes: - don't flush DB for fast color clears - don't flush any caches for initial clears - remove the flag from si_copy_buffer, always assume shader coherency Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove needless cache flushes at the end of CP DMA operationsMarek Olšák2016-04-281-8/+0
| | | | | | not needed AFAIK Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove flushes at the beginning and end of IBs done by the kernelMarek Olšák2016-04-281-12/+12
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* nir: rename lower_flrp to lower_flrp32Samuel Iglesias Gonsálvez2016-04-282-2/+2
| | | | | | | A later patch will add lower_flrp64 option to NIR. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radeonsi: check if value is negativeJakob Sinclair2016-04-281-1/+4
| | | | | | | | | | | Fixes a Coverity defect by adding checks to see if a value is negative before using it to index an array. By checking the value first it makes the code a bit safer but overall should not have a big impact. CID: 1355598 Signed-off-by: Jakob Sinclair <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* llvmpipe: s/Elements/ARRAY_SIZE/Brian Paul2016-04-2712-54/+54
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* softpipe: s/Elements/ARRAY_SIZE/Brian Paul2016-04-277-27/+27
| | | | | | | Try to standardize on the later, which is defined in the common util/ directory. Reviewed-by: Jose Fonseca <[email protected]>
* winsys/radeon: remove use_reusable_pool parameter from buffer_createNicolai Hähnle2016-04-277-8/+6
| | | | | | All callers set this parameter to true. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: remove use_reusable_pool parameter from r600_init_resourceNicolai Hähnle2016-04-275-9/+7
| | | | | | All callers set it to true. Reviewed-by: Marek Olšák <[email protected]>
* radeon/video: always use the reusable buffer poolNicolai Hähnle2016-04-274-5/+5
| | | | | | | | | | | A semantic error was introduced in a past refactoring that caused the bind parameter to be passed into the use_reusable_pool parameter of buffer_create. Since this clearly makes no sense, and there is no clear reason why the cache _shouldn't_ be used, just use the cache always. Cc: Christian König <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: work around an MSAA fast stencil clear problemNicolai Hähnle2016-04-271-3/+15
| | | | | | | | A piglit test (arb_texture_multisample-stencil-clear) has been sent. This problem was discovered analyzing Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93767 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: expclear must be disabled on first Z/S clearNicolai Hähnle2016-04-271-2/+2
| | | | | | The documentation and the HW team say so. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move blend choice out of loop in si_blit_decompress_colorNicolai Hähnle2016-04-271-9/+9
| | | | | | It does not depend on the level or layer. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use level mask for early out in si_blit_decompress_colorNicolai Hähnle2016-04-271-6/+8
| | | | | | | | Mostly for consistency with the other decompress functions, but note that in the non-DCC decompress case, the function can now early-out in slightly more (albeit probably rare) cases. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: si_blit_decompress_depth is only used for stagingNicolai Hähnle2016-04-271-21/+5
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: only decompress the required ZS planes from si_blitNicolai Hähnle2016-04-271-6/+7
| | | | | | | | | This happens to "fix" a rendering bug in KotOR2, because it avoids a still not quite understood bug with MSAA fast stencil clear decompress. For the stencil clear bug, I have sent a piglit test (arb_texture_multisample-stencil-clear). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93767 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: decompress Z & S planes in one passNicolai Hähnle2016-04-271-28/+73
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: early out of si_blit_decompress_depth_in_place based on dirty maskNicolai Hähnle2016-04-271-6/+14
| | | | | | Avoid dirtying the db_render_state atom when possible. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use MIN2 instead of expanded ?: operatorNicolai Hähnle2016-04-271-3/+3
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix brace styleNicolai Hähnle2016-04-271-2/+4
| | | | Reviewed-by: Marek Olšák <[email protected]>
* swr: s/Elements/ARRAY_SIZE/Tim Rowley2016-04-273-7/+7
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* radeonsi: emit s_waitcnt for shader memory barriers and volatileNicolai Hähnle2016-04-271-13/+23
| | | | | | | | | Turns out that this is needed after all to satisfy some strengthened coherency tests. Depends on support in LLVM, added in r267729. v2: updated to reflect changes to the LLVM intrinsic Reviewed-by: Marek Olšák <[email protected]> (v1)
* swr: [rasterizer] warning cleanupTim Rowley2016-04-279-74/+27
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] implement legacy depth bias enableTim Rowley2016-04-274-21/+25
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer jitter] support for dumping x86 asmTim Rowley2016-04-272-0/+50
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] more backend refactoringTim Rowley2016-04-278-963/+573
| | | | | | | | | BackendPixelRate should be easier to read/maintain now hopefully. Small perf bump by moving some of the pfn's to inline functions without template params. Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer jitter] add mSimdInt1TyTim Rowley2016-04-272-0/+2
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] backend refactorTim Rowley2016-04-275-238/+633
| | | | | | | Lump all template args into a bundle of traits, and add some functionality to the MSAA traits. Reviewed-by: Bruce Cherniak <[email protected]>
* svga: use the SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS queryBrian Paul2016-04-271-0/+3
| | | | | | | | | | | Instead of a hard-coded 512. The query typically returns 65536 now. Fall back to 512 if the query fails as we do for vertex shaders (which should never happen). Note that we don't actually enforce this limit in our shaders but it gets reported via the glGetProgramivARB(GL_MAX_PROGRAM_INSTRUCTIONS_ARB) query. Reviewed-by: Charmaine Lee <[email protected]>
* nouveau: codegen: LOAD: Take src swizzle into accountHans de Goede2016-04-271-2/+6
| | | | | | | | | | | | | | | | | | | | | | The llvm TGSI backend uses pointers in registers and does things like: LOAD TEMP[0].y, MEMORY[0], TEMP[0] Expecting the data at address TEMP[0].x to get loaded to TEMP[0].y. But this will cause the data at TEMP[0].x + 4 to be loaded instead. This commit adds support for a swizzle suffix for the 1st source operand, which allows using: LOAD TEMP[0].y, MEMORY[0].xxxx, TEMP[0] And actually getting the desired behavior Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nouveau: codegen: LOAD: Do not call fetchSrc(1) if the address is immediateHans de Goede2016-04-271-2/+3
| | | | | | | | | | "off" later gets set to NULL when the address is immediate, so move the fetchSrc(1) call to the non-immediate branch of the if-else. This brings handleLOAD's offset handling inline with how it is done in handleSTORE. Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nouveau: codegen: LOAD: Always use component 0 when getting the addressHans de Goede2016-04-271-1/+3
| | | | | | | | | | LOAD loads upto 4 components from the specified resource starting at the passed in x value of the 2nd source operand, the y, z and w components of the address should not be used. Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* r600g: fix and optimize tgsi_cmp when using ABS and NEG modifierPatrick Rudolph2016-04-271-1/+10
| | | | | | | | | | | | | | Some apps set NEG and ABS on the source param to test for zero. Use ALU_OP3_CNDE insted of ALU_OP3_CNDGE and unset both modifiers. It also removes the need for a MOV instruction, as ABS isn't supported on op3. Tested on AMD CAYMAN and AMD RV770. Signed-off-by: Patrick Rudolph <[email protected]> Cc: [email protected] Signed-off-by: Dave Airlie <[email protected]>
* softpipe: add support for compute shaders. (v2)Dave Airlie2016-04-278-3/+369
| | | | | | | | | | | | | | | | | This enables ARB_compute_shader on softpipe. I've only tested this with piglit so far, and I hopefully plan on integrating it with my vulkan work. I'll get to testing it with deqp more later. The basic premise is to create up to 1024 restartable TGSI machines, and execute workgroups of those machines. v1.1: free machines. v2: deqp fixes - add samplers support, finish atomic operations, fix load/store writemasks. Acked-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-11 21:43:18 +0000