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* autotools: Add passes.h to sources so it will be included in the tarballDylan Baker2018-04-201-0/+1
| | | | | | | | | | | This was introduced in commit 8f848ada8a42d9aaa8136afa1bafe32281a0fb48 but not added to the sources list, which is necessary for it to be included in release tarballs. Fixes: 8f848ada8a42d9aaa8136afa1bafe32281a0fb48 ("swr/rast: Start refactoring of builder/packetizer.") Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nvc0: fix line width on GM20x+Rhys Perry2018-04-201-1/+4
| | | | | | | This has the side-effect of fixing polygon-offset piglit test failures. Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* etnaviv: fix texture_format_needs_swizLucas Stach2018-04-201-1/+1
| | | | | | | | | | | | | memcmp returns 0 when both swizzles are the same, which means we don't need any hardware swizzling. texture_format_needs_swiz should return true when the return value of the memcmp is non-zero. Fixes: 751ae6afbefd ("etnaviv: add support for swizzled texture formats") Cc: [email protected] Signed-off-by: Lucas Stach <[email protected]> Tested-by: Marek Vasut <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]>
* radeonsi: generate image load/store/atomic ops using ac_build_image_opcodeNicolai Hähnle2018-04-201-131/+99
| | | | | | In preparation of dimension-aware LLVM image intrinsics. Acked-by: Marek Olšák <[email protected]>
* amd/common: pass address components individually to ac_build_image_intrinsicNicolai Hähnle2018-04-201-144/+78
| | | | | | This is in preparation for the new image intrinsics. Acked-by: Marek Olšák <[email protected]>
* amd/common: pass new enum ac_image_dim to ac_build_image_opcodeNicolai Hähnle2018-04-201-2/+48
| | | | | | | This is in preparation for the new, dimension-aware LLVM image intrinsics. Acked-by: Marek Olšák <[email protected]>
* radeonsi/nir: fix crash in test involving the sample maskNicolai Hähnle2018-04-201-1/+2
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi/nir: set FS properties only when scanning a fragment shaderNicolai Hähnle2018-04-201-1/+2
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: fix error paths of si_texture_transfer_mapNicolai Hähnle2018-04-201-13/+12
| | | | | | | trans is zero-initialized, but trans->resource is setup immediately so needs to be dereferenced. Reviewed-by: Timothy Arceri <[email protected]>
* nir: Offset vertex_id by first_vertex instead of base_vertexNeil Roberts2018-04-193-5/+4
| | | | | | | | | | | | | | | | | | base_vertex will be zero for non-indexed calls and in that case we need vertex_id to be offset by the ‘first’ parameter instead. That is what we get with first_vertex. This is true for both GL and Vulkan. The freedreno driver is also setting vertex_id_zero_based on nir_options. In order to avoid breakage this patch switches the relevant code to handle SYSTEM_VALUE_FIRST_VERTEX so that it can retain the same behavior. v2: change a3xx/fd3_emit.c and a4xx/fd4_emit.c from SYSTEM_VALUE_BASE_VERTEX to SYSTEM_VALUE_FIRST_VERTEX (Kenneth). Reviewed-by: Ian Romanick <[email protected]> Cc: Rob Clark <[email protected]> Acked-by: Marek Olšák <[email protected]>
* svga: Fix incorrect advertizing of EGL_KHR_gl_colorspaceThomas Hellstrom2018-04-191-1/+1
| | | | | | | | | | | | | | | | | | | When advertizing this extension, egl_dri2 uses the DRI2_RENDERER_QUERY extension to query whether an sRGB format is supported. That extension will query our driver with the BIND flag PIPE_BIND_RENDER_TARGET rather than PIPE_BIND_DISPLAY_TARGET which is used when building the configs. We only return the correct value for PIPE_BIND_DISPLAY_TARGET. The inconsistency causes EGL to crash at surface initialization if sRGB is not supported. Fix this by supporting both bind flags. Testing done: piglit egl_gl_colorspace srgb Cc: <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* swr: Fix include for createPromoteMemoryToRegisterPassMike Lothian2018-04-191-0/+3
| | | | | | | | | | | | Include llvm/Transforms/Utils.h with the newest LLVM 7 v2: Include with " " rather than < > (Vinson Lee) v3: Use LLVM_VERSION_MAJOR rather than HAVE_LLVM (George Kyriazis) Signed-of-by: Mike Lothian <[email protected]> Tested-by: Vinson Lee <[email protected]> Reviewed-By: George Kyriazis <[email protected]>
* radeon/vce: disable vce dual pipe on VegaMLeo Liu2018-04-181-1/+2
| | | | Acked-by: Nicolai Hähnle <[email protected]>
* radeonsi: add support for VegaMMarek Olšák2018-04-185-2/+10
| | | | Acked-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix a hang with an empty first IBMarek Olšák2018-04-181-3/+4
| | | | | | | | This packet causes the no-op IB detection to fail, so the IB is always submitted. Also fix the no-op IB detection by moving the begin call. Cc: 18.0 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* swr/rast: Fix VGATHERPD loweringGeorge Kyriazis2018-04-181-13/+69
| | | | | | Also Implement VHSUBPS in x86 lowering pass. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Replace x86 VMOVMSK with llvm-only implementationGeorge Kyriazis2018-04-185-5/+26
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Optimize late/bindless JIT of samplersGeorge Kyriazis2018-04-1825-105/+213
| | | | | | | | | Add per-worker thread private data to all shader calls Add per-worker sampler cache and jit context Add late LoadTexel JIT support Add per-worker-thread Sampler / LoadTexel JIT Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Implement VROUND intrinsic in x86 lowering passGeorge Kyriazis2018-04-181-1/+37
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Refactor to improve code sharing.George Kyriazis2018-04-181-43/+36
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: minimize codegen redundant workGeorge Kyriazis2018-04-186-128/+335
| | | | | | Move filtering of redundant codegen operations into gen scripts themselves Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: double-pump in x86 lowering passGeorge Kyriazis2018-04-181-11/+19
| | | | | | Add support for double-pumping a smaller SIMD width intrinsic. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Fix 64bit float loads in x86 lowering passGeorge Kyriazis2018-04-182-45/+25
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add shader stats infrastructure (WIP)George Kyriazis2018-04-184-34/+148
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Type-check TemplateArgUnrollerGeorge Kyriazis2018-04-181-18/+21
| | | | | | Allows direct use of enum values in conversion to template args. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add vgather to x86 lowering pass.George Kyriazis2018-04-181-9/+76
| | | | | | Add support for generic VGATHERPD intrinsic in x86 lowering pass. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: fix commentGeorge Kyriazis2018-04-181-1/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: add cvt instructions in x86 lowering passGeorge Kyriazis2018-04-185-59/+48
| | | | | | Support generic VCVTPD2PS and VCVTPH2PS in x86 lowering pass. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Fix alloca usage in jitterGeorge Kyriazis2018-04-183-0/+20
| | | | | | | | Fix issue where temporary allocas were getting hoisted to function entry unnecessarily. We now explicitly mark temporary allocas and skip hoisting during the hoist pass. Shuold reduce stack usage. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Change gfx pointers to gfxptr_tGeorge Kyriazis2018-04-1811-103/+220
| | | | | | | Changing type to gfxptr for indices and related changes to fetch and mem builder code. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Fix byte offset for non-indexed drawsGeorge Kyriazis2018-04-181-2/+3
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add support for setting optimization levelGeorge Kyriazis2018-04-189-18/+55
| | | | | | for JIT compilation Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Adding translate call to builder_gfx_mem.George Kyriazis2018-04-182-0/+7
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Fix codegen for typedef typesGeorge Kyriazis2018-04-181-0/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: add x86 lowering pass to fragment shaderGeorge Kyriazis2018-04-181-0/+7
| | | | | | | | Needed because some FP paths (namely stipple) use gather intrinsics that now need to be lowered to x86. v2: fix typo in commit message Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Enable generalized fetch jitGeorge Kyriazis2018-04-185-1103/+139
| | | | | | | | | Enable generalized fetch jit with 8 or 16 wide SIMD target. Still some work needed to remove some simd8 double pumping for 16-wide target. Also removed unused non-gather load vertices path. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add builder_gfx_mem.{h|cpp}George Kyriazis2018-04-185-4/+210
| | | | | | | | | Abstract usage scenarios for memory accesses into builder_gfx_mem. Builder_gfx_mem will convert gfxptr_t from 64-bit int to regular pointer types for use by builder_mem. v2: reworded commit message; renamed enum more appropriately Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Lower VGATHERPS and VGATHERPS_16 to x86.George Kyriazis2018-04-181-67/+2
| | | | | | | Some more work to do before we can support simultaneous 8-wide and 16-wide and remove the VGATHERPS_16 version. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Cleanup of JitManager convenience typesGeorge Kyriazis2018-04-184-44/+5
| | | | | | | Small cleanup. Remove convenience types from JitManager and standardize on the Builder's convenience types. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Lower PERMD and PERMPS to x86.George Kyriazis2018-04-184-86/+14
| | | | | | | Add support for providing an emulation callback function for arch/width combinations that don't map cleanly to an x86 intrinsic. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Start refactoring of builder/packetizer.George Kyriazis2018-04-1816-46/+565
| | | | | | | | | | | Move x86 intrinsic lowering to a separate pass. Builder now instantiates generic intrinsics for features not supported by llvm. The separate x86 lowering pass is responsible for lowering to valid x86 for the target SIMD architecture. Currently it's a port of existing code to get it up and running quickly. Will eventually support optimized x86 for AVX, AVX2 and AVX512. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Simplify #define usage in gen source fileGeorge Kyriazis2018-04-181-4/+3
| | | | | | | | | | | | Removed preprocessor defines from structures passed to LLVM jitted code. The python scripts do not understand the preprocessor defines and ignores them. So for fields that are compiled out due to a preprocessor define the LLVM script accounts for them anyway because it doesn't know what the defines are set to. The sanitize defines for open source are fine in that they're safely used. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Move CallPrint() to a separate fileGeorge Kyriazis2018-04-184-21/+56
| | | | | | Needed work for jit code debug. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Fix name mangling for LLVM pow intrinsicGeorge Kyriazis2018-04-181-1/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add some archrast countersGeorge Kyriazis2018-04-187-4/+53
| | | | | | Hook up archrast counters for shader stats: instructions executed. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Code cleanupGeorge Kyriazis2018-04-181-8/+1
| | | | | | Removing some code that doesn't seem to do anything meaningful. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add "Num Instructions Executed" stats intrinsic.George Kyriazis2018-04-181-7/+21
| | | | | | | Added a SWR_SHADER_STATS structure which is passed to each shader. The stats pass will instrument the shader to populate this. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add MEM_ADD helper function to Builder.George Kyriazis2018-04-182-0/+9
| | | | | | | | mem[offset] += value This function will be heavily used by all stats intrinsics. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Permute work for simd16George Kyriazis2018-04-187-10/+67
| | | | | | | | Fix slow permutes in PA tri lists under SIMD16 emulation on AVX Added missing permute (interlane, immediate) to SIMDLIB Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: WIP builder rewrite (2)George Kyriazis2018-04-181-4/+13
| | | | | | | | | | | | | Finish up the remaining explicit intrinsic uses. At this point all explicit Intrinsic::getDeclaration() usage has been replaced with auto generated macros generated with gen_llvm_ir_macros.py. Going forward, make sure to only use the intrinsics here, adding new ones as needed. Next step is to remove all references to x86 intrinsics to keep the builder target-independent. Any x86 lowering will be handled by a separate pass. Reviewed-by: Bruce Cherniak <[email protected]>
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