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* winsys/amdgpu: make IBs writable and expose their addressMarek Olšák2019-04-231-0/+1
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* ac: add radeon_info::marketing_name, replacing the winsys callbackMarek Olšák2019-04-233-26/+4
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* tgsi/scan: add uses_drawidMarek Olšák2019-04-231-0/+3
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* iris: Track valid data range and infer unsynchronized mappings.Kenneth Graunke2019-04-235-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | Applications frequently call glBufferSubData() to consecutive regions of a VBO to append new vertex data. If no data exists there yet, we can promote these to unsynchronized writes, even if the buffer is busy, since the GPU can't be doing anything useful with undefined content. This can avoid a bunch of unnecessary blitting on the GPU. u_threaded_context would do this for us, and in fact prohibits us from doing so (see TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED). But we haven't hooked that up yet, and it may be useful to disable u_threaded_context when debugging...at which point we'd still want this optimization. At the very least, it would let us measure the benefit of threading independently from this optimization. And it's not a lot of code. Removes most stall avoidance blits in "Total War: WARHAMMER." On my Skylake GT4e at 1920x1080, this appears to improve performance in games by the following (but I did not do many runs for proper statistics gathering): ---------------------------------------------- | DiRT Rally | +2% (avg) | + 2% (max) | | Bioshock Infinite | +3% (avg) | + 9% (max) | | Shadow of Mordor | +7% (avg) | +20% (max) | ----------------------------------------------
* iris: Make a resource_is_busy() helperKenneth Graunke2019-04-231-4/+13
| | | | This checks both "is it busy" and "do we have work queued up for it"?
* iris: Replace buffer backing storage and rebind to update addresses.Kenneth Graunke2019-04-234-5/+171
| | | | | | | | | | | | | | | | This implements PIPE_CAP_INVALIDATE_BUFFER and invalidate_resource(), as well as the PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE flag. When either of these happen, we swap out the backing storage of the buffer for a new idle BO, allowing us to write to it immediately without stalling or queueing a blit. On my Skylake GT4e at 1920x1080, this improves performance in games: ----------------------------------------------- | DiRT Rally | +25% (avg) | +17% (max) | | Bioshock Infinite | +22% (avg) | +11% (max) | | Shadow of Mordor | +27% (avg) | +83% (max) | -----------------------------------------------
* iris: Make memzone_for_address non-staticKenneth Graunke2019-04-232-5/+7
| | | | I want to use this in iris_resource.c.
* iris: Make a gl_shader_stage -> pipe_shader_stage helper functionKenneth Graunke2019-04-231-0/+14
| | | | | | This is probably not the best place for it, but I don't feel like moving the one out of the TGSI translator today, and we already have the other direction here, so...*shrug*
* iris: Rework image views to store pipe_image_view.Kenneth Graunke2019-04-234-35/+52
| | | | This will be useful when rebinding images.
* iris: Rework UBOs and SSBOs to use pipe_shader_bufferKenneth Graunke2019-04-232-104/+71
| | | | | | This unifies a bunch of the UBO and SSBO code to use common structures. Beyond iris_state_ref, pipe_shader_buffer also gives us a buffer size, which can be useful when filling out the surface state.
* iris: Track bound constant buffersKenneth Graunke2019-04-232-0/+6
| | | | | This helps avoid having to iterate over [0, PIPE_MAX_CONSTANT_BUFFERS) looking to see if any resources are bound.
* iris: Mark constants dirty on transfer unmap even if no flushes occurKenneth Graunke2019-04-231-2/+8
| | | | | | | | | | | | I have various conditions in place to try and avoid unnecessary PIPE_CONTROL flushes, especially to batches which may have never used the buffer being mapped. But if we do a CPU map to a bound constant buffer, we still need to mark push constants dirty, even if there's nothing happening in batches that would warrant a flush. Fixes obvious misrendering in the "XCOM 2: War of the Chosen" menus (lots of rainbow colored triangles). Fixes lots of blinking elements in "Shadow of Mordor". Fixes missing crowd rendering in "DiRT Rally".
* radeonsi: use CP DMA for the null const buffer clear on CIKMarek Olšák2019-04-225-10/+16
| | | | | | | | | | This is a workaround for a thread deadlock that I have no idea why it occurs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108879 Fixes: 9b331e462e5021d994859756d46cd2519d9c9c6e Acked-by: Samuel Pitoiset <[email protected]>
* iris: Track bound and writable SSBOsKenneth Graunke2019-04-222-1/+16
| | | | | | | | | Marek recently extended pipe->set_shader_buffers() to take an extra writable_bitmask parameter, indicating which SSBOs are writable (some may be bound read-only). We can use this to decide whether to set EXEC_OBJECT_WRITE when pinning. Avoiding the write flag can save us some cross-batch flushing if the SSBO is used for reading in both the render and compute engines.
* virgl: clear vertex_array_dirtyChia-I Wu2019-04-221-0/+2
| | | | | | | Clear vertex_array_dirty after the state is emitted. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* iris: Enable the dual_color_blend_by_location driconf option.Kenneth Graunke2019-04-224-0/+24
| | | | This fixes rendering in Unigine Valley 1.0 and Heaven 4.0.
* iris: Add mechanism for iris-specific driconf optionsKenneth Graunke2019-04-226-3/+42
| | | | | | Based on Nicolai's 0f8c5de8690e7c87aa2e24383065efaca7e6fe78. Reviewed-by: Dylan Baker <[email protected]>
* lima: add Android buildIcenowy Zheng2019-04-211-0/+88
| | | | | | | | | Currently only meson build supported is added for lima driver. Add Android build support for lima. Signed-off-by: Icenowy Zheng <[email protected]> Acked-by: Qiang Yu <[email protected]>
* panfrost/mdg: Use shared fsign loweringAlyssa Rosenzweig2019-04-194-11/+4
| | | | | | Fixes failures in shaders.operator.common_functions.sign.* Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Fixup vertex offsets to prevent shadow copyAlyssa Rosenzweig2019-04-192-43/+67
| | | | | | | | | | | Mali attribute buffers have to be 64-byte aligned. However, Gallium enforces no such requirement; for unaligned buffers, we were previously forced to create a shadow copy (slow!). To prevent this, we instead use the offseted buffer's address with the lower bits masked off, and then add those masked off bits to the src_offset. Proof of correctness included, possibly for the opportunity to say "QED" unironically. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Track BO lifetime with jobs and reference countsAlyssa Rosenzweig2019-04-199-37/+207
| | | | | | | | | | | | | | | | | | | | This (fairly large) patch continues work surrounding the panfrost_job abstraction to improve job lifetime management. In particular, we add infrastructure to track which BOs are used by a particular job (currently limited to the vertex buffer BOs), to reference count these BOs, and to automatically manage the BOs memory based on the reference count. This set of changes serves as a code cleanup, as a way of future proofing for allowing flushing BOs, and immediately as a bugfix to workaround the missing reference counting for vertex buffer BOs. Meanwhile, there are a few cleanups to vertex buffer handling code itself, so in the short-term, this allows us to remove the costly VBO staging workaround, since this patch addresses the underlying causes. v2: Use pipe_reference for BO reference counting, rather than managing it ourselves. Don't duplicate hash-table key removal. Fix vertex buffer counting. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* lima: enable nir fsign lowering in ppirErico Nunes2019-04-191-0/+1
| | | | | | | | The mali utgard pp doesn't support a sign instruction. Use the nir lowering function for fsign to implement fsign in ppir. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* lima/ppir: support ppir_op_ceilErico Nunes2019-04-193-0/+14
| | | | | | | | | Add a few missing ppir_op_ceil enum handling entries to implement nir_op_fceil in lima ppir. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* iris: Be less aggressive at postdraw work skippingKenneth Graunke2019-04-181-28/+36
| | | | | | | | | | | | | | | | We empty the cache sets when flushing the batch, at which point we need to add any framebuffer related BOs even though the bindings haven't changed. So, we now do the cache set tracking unconditionally. For now, we continue skipping resolve work based on the same conditions in the predraw functions - the thinking is if we didn't trigger resolves, there's nothing to update here. Time will tell if this works. Partly reverts commit 365886ebe1a54f893b688b457553eead6aa572ea, and fixes Unigine Valley rendering on Gen9+. Drops drawoverhead scores by about 10-12%. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110353
* virgl: wait after a flushGurchetan Singh2019-04-183-6/+12
| | | | | | | | | | | | | | | | | We really need to wait under certain circumstances, or we can end up writing to memory the same time the host is reading. Partial revert of d6dc68 ("virgl: use uint16_t mask instead of separate booleans"). Test cases: - dEQP-GLES31.functional.texture.texture_buffer.render_modify.as_vertex_array.bufferdata on vtest protocol version 2 - Flickering during Alien Isolation Fixes: d6dc68 ("virgl: use uint16_t mask instead of separate booleans") Signed-off-by: Gurchetan Singh <[email protected]> Reviewed-By: Gert Wollny <[email protected]> Reviewed-By: Piotr Rak <[email protected]>
* radeonsi/gfx9: use the correct condition for the DPBB + QUANT_MODE workaroundMarek Olšák2019-04-181-4/+4
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* freedreno: Fix format string warningKristian H. Kristensen2019-04-181-1/+1
| | | | | | Modifiers are uin64_t. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Add helper for incrementing regidKristian H. Kristensen2019-04-181-1/+10
| | | | | | | Increments the regid by specified amount unless regid is is r63.x (invalid). Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno: Use enum values from matching enumKristian H. Kristensen2019-04-182-3/+3
| | | | | | | We get a couple of warnings from using mismatched enum values. This fixes that. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a2xx: Fix redundant if statementKristian H. Kristensen2019-04-181-16/+14
| | | | | | | We test the condition, declare a few variables, then test the exact same condition again. Let's not do that. Signed-off-by: Kristian H. Kristensen <[email protected]>
* iris: implement WaEnableStateCacheRedirectToCSLionel Landwerlin2019-04-181-0/+7
| | | | | | | | | | | | This 3d performance workaround was initially put in the kernel but the media driver requires different settings so the register has been whitelisted in i915 [1] and userspace drivers are left initializing it as they wish. [1] : https://patchwork.freedesktop.org/series/59494/ Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* virgl: document potentially failing blitErik Faye-Lund2019-04-171-0/+6
| | | | | | | | | This blit can fail, but this is not new; in the old version we didn't even try to blit in this case. So let's just document the limitation for now, and leave this for another day. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: do color-conversion during when mapping transferErik Faye-Lund2019-04-171-10/+70
| | | | | | | | | | | | | When running on OpenGL ES, we can't just map any format for reading, because of limitations on glReadPixels. So let's fall back to the blit code-path, and translate the pixels to the correct format in the end. This fixes the remaining failures of KHR-GL32.packed_pixels.* apart from the sRGB tests. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: only blit if resource is readErik Faye-Lund2019-04-171-2/+5
| | | | | Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: get readback-formats from hostErik Faye-Lund2019-04-173-0/+44
| | | | | Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: make sure bind is set for non-buffersErik Faye-Lund2019-04-171-0/+3
| | | | | | | Otherwise, virglrenderer will reject the resource. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: support write-back with staged transfersErik Faye-Lund2019-04-172-22/+49
| | | | | | | | | | | | | | | | We currently don't support writing to resources that uses a temporary staging-resource to resolve the pixels. If a write-bit was set, we forgot to perform a blit back to the old resource, followed by trying to update the wrong resource, which lacks backing-storage. The end-result would be that nothing useful happened. This approach also fixes a few smaller bugs, like using the wrong box (without x y and z zeroed out), which means a partial update of a multisampled texture could result in the wrong part of the texture being updated. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: use pipe_box for blit dst-rectErik Faye-Lund2019-04-171-5/+12
| | | | | Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: rewrite core of virgl_texture_transfer_mapErik Faye-Lund2019-04-171-36/+58
| | | | | Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: return error if allocating resolve_tmp failsErik Faye-Lund2019-04-171-0/+4
| | | | | Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: wait for the right resourceErik Faye-Lund2019-04-171-1/+1
| | | | | | | | In case we're resolving, we need to wait for the resolved resource instead of the original one. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: check for readback on correct resourceErik Faye-Lund2019-04-171-1/+1
| | | | | Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: make unmap queuing a bit more straight-forwardErik Faye-Lund2019-04-171-5/+7
| | | | | | | | | It's hard to read the code that decides if we want to queue up an unmap or destroy the transfer right away. So let's make it a bit simpler, by setting a bool in case we want to queue it. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: simplify virgl_texture_transfer_unmap logicErik Faye-Lund2019-04-171-13/+9
| | | | | | | | There's no reason to keep an extra indentation level here, let's merge the two if-conditions. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: track full virgl_resource instead of just virgl_hw_resErik Faye-Lund2019-04-171-5/+5
| | | | | Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: tmp_resource -> templErik Faye-Lund2019-04-171-4/+3
| | | | | | | | This isn't the temporary resource itself, it's the template that we'll create the resource from. So let's name it appropriately. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: remove pointless transfer-counterErik Faye-Lund2019-04-174-4/+2
| | | | | | | This is only written to, never read. Let's just get rid of it. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* radeonsi/nir: fix scanning of bindless imagesTimothy Arceri2019-04-171-38/+37
| | | | Fixes: d62d434fe920 ("ac/nir_to_llvm: add image bindless support")
* iris: Add texture cache flushing hacks for blit and resource_copy_regionKenneth Graunke2019-04-161-0/+36
| | | | | | | | | | | | | This is a port of Jason's 8379bff6c4456f8a77041eee225dcd44e5e00a76 from i965 to iris. We can't find anything relevant in the documentation and no one we've talked to has been able to help us pin down a solution. Unfortunately, we have to put the hack in both iris_blit() and iris_copy_region(). st/mesa's CopyImage() implementation sometimes chooses to use pipe->blit() instead of pipe->resource_copy_region(). For blits, we only do the hack if the blit source format doesn't match the underlying resource (i.e. it's reinterpreting the bits). Hopefully this should not be too common.
* iris: Change vendor and renderer stringsKenneth Graunke2019-04-161-1/+4
| | | | | | | | | | | | | | | | | This patch changes the GL_VENDOR string from "Mesa Project" to "Intel". This makes GLX_MESA_query_renderer report "Vendor: Intel (0x8086)" instead of "Vendor: Mesa Project (0x8086)" which is arguably wrong. We now also use a consistent vendor string across Windows and Linux. It also prepends "Mesa" to the GL_RENDERER string, both to credit the community and have a distinguishing mark between the two drivers. We drop "DRI" compared to i965, as it's not really that important. Improves performance in Portal by 1.8x. Iris is now 3.86% faster than i965 at the portal-d1.dem timedemo on my Kabylake laptop. One change is that Portal selects the MapBufferRange path based on the vendor string, and iris's BufferSubData path is still missing the storage invalidation optimization.
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