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* tree-wide: remove trailing backslashEric Engestrom2017-06-073-4/+4
| | | | | | | | | Simple search for a backslash followed by two newlines. If one of the newlines were to be removed, this would cause issues, so let's just remove these trailing backslashes. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* radeonsi: fix a GPU hang with tessellation on 2-CU configsMarek Olšák2017-06-061-1/+5
| | | | | | | | | Only harvested Stoney has 2 CUs. Tested on 2-CU Stoney and Fiji forced to 2 CUs. Cc: 17.0 17.1 <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeon: remove out of date LLVM_REVISION.txtEmil Velikov2017-06-052-4/+0
| | | | | | | | | | | | The file was introduced to track which LLVM revision was required, yet that has quickly gone out of shape. It has seen no updates since 2013. Cc: Nicolai Hähnle <[email protected]> Cc: Marek Olšák <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Aaron Watry <[email protected]>
* r600: refactor out some compressed resource state code.Dave Airlie2017-06-061-24/+28
| | | | | | | This just takes this out to a separate function as it will get more complex with images. Reviewed-by: Glenn Kennard <[email protected]>
* r600: document some of the missing shader constants.Dave Airlie2017-06-061-0/+4
| | | | | | These are used for fragment shader thread calculations. Reviewed-by: Glenn Kennard <[email protected]>
* r600: add register info for atomic counters.Dave Airlie2017-06-062-0/+51
| | | | | | | | | The atomic counters on evergreen are implemented via append/consume UAV counters. This just adds the register info for them. The EOS packets are used to get the atomic totals extracted post shader execution for storing into a buffer. Reviewed-by: Glenn Kennard <[email protected]>
* r600: add missing RAT registers and operations.Dave Airlie2017-06-063-0/+59
| | | | | | | | | | This just documents in the headers the RAT operation list, and the RAT encoding for exports. The immediate registers are used to point to buffers for the RAT return values (_RTN instructions). Reviewed-by: Glenn Kennard <[email protected]>
* r600/sb: fix typo in field definitionsDave Airlie2017-06-061-1/+1
| | | | Pointed out by glennk.
* r600: fix incorrect and missing bit field in register headers.Dave Airlie2017-06-051-3/+4
| | | | | The compression field was incorrect, and we were missing the depth before shader field.
* nvc0: Add support for ARB_post_depth_coverageLyude2017-06-028-1/+15
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: Add a cap to check if the driver supports ARB_post_depth_coverageLyude2017-06-0215-0/+15
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: disable BGRA8 images on FermiLyude2017-06-021-5/+14
| | | | | | | | | | | | BGRA8 image stores on Fermi don't work, which results in breaking PBO downloads, such that they always return 0x0. Discovered this through a glamor bug, and confirmed it does indeed break a good number of piglit tests such as spec/arb_pixel_buffer_object/pbo-read-argb8888 Fixes: 8e7893eb53213 ("nvc0: add support for BGRA8 images") Signed-off-by: Lyude <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* etnaviv: always do cpu_fini in transfer_unmapLucas Stach2017-06-011-3/+6
| | | | | | | | | | | | | | | | | The cpu_fini() call pushes the buffer back into the GPU domain, which needs to be done for all buffers, not just the ones with CPU written content. The etnaviv kernel driver currently doesn't validate this, but may start to do so at a later point in time. If there is a temporary resource the fini needs to happen before the RS uses this one as the source for the upload. Also remove an invalid comment about flushing CPU caches, cpu_fini takes care of everything involved in this. Fixes: c9e8b49b885 ("etnaviv: gallium driver for Vivante GPUs") Cc: [email protected] Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Philipp Zabel <[email protected]> Reviewed-By: Wladimir J. van der Laan <[email protected]>
* nvc0: Clean up unnecessary includes from gallium/auxiliary/vl/Rhys Kidd2017-06-011-3/+0
| | | | | Signed-off-by: Rhys Kidd <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* r600/eg: add support for tracing IBs after a hang.Dave Airlie2017-06-0111-7/+785
| | | | | | | | | This is a poor man's version of radeonsi ddebug stuff, this should get hooked into that infrastructure, and grow more stuff, but for now, just create R600_TRACE var that points to a file that you want to dump the last IB to. Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: remove unused si_pm4_state::compute_pktSamuel Pitoiset2017-05-312-4/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: remove chip_class define from si_pm4.hSamuel Pitoiset2017-05-311-1/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: merge si_pm4_free_state_simple() into si_pm4_free_state()Samuel Pitoiset2017-05-312-8/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* freedreno/a5xx: drop WFIs in emit_marker5()Rob Clark2017-05-301-5/+0
| | | | | | | | | Results in always having at least one WFI between draws, which was slowing stk down by ~5% and ~10% in xonotic. (also drop bogus assert while we're at it.) Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: timestamp / time-elapsed queriesRob Clark2017-05-302-1/+97
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: rename query result structRob Clark2017-05-301-23/+22
| | | | | | Going to want the same thing for timestamp queries. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-05-306-18/+624
| | | | Signed-off-by: Rob Clark <[email protected]>
* swr/rast: code cleanup (no functional change)Tim Rowley2017-05-301-2/+6
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: whitespace changesTim Rowley2017-05-303-8/+3
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: code cleanup (no functional change)Tim Rowley2017-05-301-3/+4
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: allow early-z if shader uses depth valueTim Rowley2017-05-301-1/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: move wireframe/point triangle binning after cullingTim Rowley2017-05-301-80/+76
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: remove unused functionsTim Rowley2017-05-301-28/+0
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: code cleanup (no functional change)Tim Rowley2017-05-301-60/+64
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: move binner utility functions to binner.hTim Rowley2017-05-303-193/+225
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 FE - fix/use SIMD16 calcDeterminantIntVertical()Tim Rowley2017-05-303-43/+65
| | | | | | Stop double pumping the SIMD8 version. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: add renderTargetArrayIndex to SWR_PS_CONTEXTTim Rowley2017-05-302-5/+6
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: make simd16 logicops avx512f safeTim Rowley2017-05-301-4/+10
| | | | | | Express the simd16 logicops in terms of avx512f instructions. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 FE - add SIMD16 types to jitterTim Rowley2017-05-303-10/+11
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 FE - fix PA_STATE_OP::Reset()Tim Rowley2017-05-301-0/+3
| | | | | | Fixes instanced GS. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 FE - simplify/refactor StreamOutTim Rowley2017-05-301-42/+0
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 FE - fix conservative rasterizationTim Rowley2017-05-301-0/+32
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 FE - interleaved simdvertex output in GSTim Rowley2017-05-302-20/+31
| | | | | | Eliminates conversion copies on GS output from simdvertex to simd16vertex. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: fix _simd16_movemask_(ps,pd) native AVX512 intrinsicsTim Rowley2017-05-301-4/+4
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 FE - primitive assembly simplificationTim Rowley2017-05-302-50/+32
| | | | | | | | | | | Reduce/simplify vertex storage usage in PA_STATE_OPT, fix PA GetNextVSOutput wrap-around behaviour and eliminate unnecessary SIMDVERTEX copies/storage for tri fan in PA_STATE_OPT Fixes the OpenGL tri fan test failure under SIMD16 - triangle-rasterization-overdraw. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: silence write of cfg graphTim Rowley2017-05-301-3/+3
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: add CreateDirectoryPath to recursively create directoriesTim Rowley2017-05-303-8/+53
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: add support for DX1_RGB{_SRGB} formatsTim Rowley2017-05-303-37/+93
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: clean up whitespaceTim Rowley2017-05-301-1/+0
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: adjust BinPostSetupPoints* function signatureTim Rowley2017-05-301-3/+3
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: remove extra pixel center adjustment in BinPostSetupPointsTim Rowley2017-05-301-5/+0
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* nvc0: support for GP10BAlexandre Courbot2017-05-301-0/+1
| | | | | | | | GP10B uses the same 3D class as GP100. Signed-off-by: Alexandre Courbot <[email protected]> Acked-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* etnaviv: Don't try to use the index buffer if size is zeroTomeu Vizoso2017-05-301-11/+13
| | | | | | | | | | | | | If info->index_size is zero, info->index will point to uninitialized memory. Fatal signal 11 (SIGSEGV), code 2, fault addr 0xab5d07a3 in tid 20456 (surfaceflinger) lst: Remove useless indexbuf conditional in the index_size != 0 case. Fixes: 330d0607ed60 ("gallium: remove pipe_index_buffer and set_index_buffer") Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* radeonsi: use ac_build_buffer_load for shader buffer loadsMarek Olšák2017-05-291-22/+21
| | | | | | and document why we can't use SMEM yet. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move building llvm.SI.load.const into ac_build_buffer_loadMarek Olšák2017-05-291-13/+10
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
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