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* gallium/util: replace pipe_condvar_broadcast() with cnd_broadcast()Timothy Arceri2017-03-072-4/+4
| | | | | | | pipe_condvar_broadcast() was made unnecessary with fd33a6bcd7f12. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/util: replace pipe_condvar_wait() with cnd_wait()Timothy Arceri2017-03-072-2/+2
| | | | | | | pipe_condvar_wait() was made unnecessary with fd33a6bcd7f12. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/util: replace pipe_condvar_destroy() with cnd_destroy()Timothy Arceri2017-03-071-1/+1
| | | | | | | pipe_condvar_destroy() was made unnecessary with fd33a6bcd7f12. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/util: replace pipe_condvar_init() with cnd_init()Timothy Arceri2017-03-072-2/+2
| | | | | | | pipe_condvar_init() was made unnecessary with fd33a6bcd7f12. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: don't monitor SDMA busyness on EG/Cayman/SIMarek Olšák2017-03-061-1/+1
| | | | | | | | It's always busy. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99955 Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: drop support for LLVM 3.6 & 3.7Marek Olšák2017-03-065-28/+9
| | | | | | They are too old. Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: set the convergent attribute where neededMarek Olšák2017-03-061-1/+1
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: fix LLVM 3.9 - don't use non-matching attributes on declarationsMarek Olšák2017-03-061-2/+4
| | | | | | | | | Call site attributes are used since LLVM 4.0. This also reverts commit b19caecbd6f310c1663b0cfe483d113ae3bd5fe2 "radeon/ac: fix intrinsic version check", because this is the correct fix. Reviewed-by: Dave Airlie <[email protected]>
* swr: [rasterizer core] fix primID provoking vertex for GSTim Rowley2017-03-051-2/+2
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: implement geometry shadersTim Rowley2017-03-0513-63/+700
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* svga: pass NULL to ureg_get_tokens()Timothy Arceri2017-03-052-6/+3
| | | | | | | The number of tokens in never used and the pointer is NULL checked so just pass NULL. Reviewed-by: Brian Paul <[email protected]>
* nvc0: take extra pushbuf space into account for pushbuf_space callsIlia Mirkin2017-03-041-2/+2
| | | | | | | | | | | | | | | | | See detailed explanation of why this is needed in commit eb60a89bc3a. This spot was missed/overlooked. Basically as a result of the fact that BEGIN_* ends up calling PUSH_SPACE, which in turn adds an extra 8 to the requested amount, we have to be mindful of that when doing bare nouveau_pushbuf_space calls. Reportedly this fixes some crashes when replaying a hitman trace taken on radeonsi. Fixes: eb60a89bc3a ("nouveau: take extra push space into account for pushbuf_space calls") Cc: "13.0 17.0" <[email protected]> Reported-by: Karol Herbst <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nvc0: increase alignment to 256 for texture buffers on fermiIlia Mirkin2017-03-041-1/+3
| | | | | | | | | | When binding as textures, the alignment can be 16. However when binding as an image, the address has to be aligned to 256. (Also when binding as an RT, but that can't happen with GL or current gallium APIs.) Reported-by: Roy Spliet <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> Acked-by: Samuel Pitoiset <[email protected]>
* ac: normalize build helper namesMarek Olšák2017-03-033-35/+35
| | | | | | s/emit/build/ Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: move SI.vs.load.input building into amd/commonMarek Olšák2017-03-031-15/+10
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: detect and mark loads/stores from read-only/write-only memoryMarek Olšák2017-03-031-10/+105
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* ac: replace llvm.SI.tbuffer.store with llvm.amdgcn.buffer.store if ADD_TID=0Marek Olšák2017-03-031-11/+11
| | | | | | | | ADD_TID doesn't work. Needs more investigation. v2: remove leftover dead code Reviewed-by: Dave Airlie <[email protected]> (v1)
* radeonsi: use the writeonly LLVM attributeMarek Olšák2017-03-031-3/+6
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* ac: remove offen parameter from ac_build_buffer_store_dwordMarek Olšák2017-03-031-13/+12
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: enable TC L2 for tessellation offchip storesMarek Olšák2017-03-031-8/+8
| | | | Vulkan does the same thing.
* radeonsi: merge and simplify tbuffer_store functionsMarek Olšák2017-03-031-40/+39
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: set noalias on input shader pointersMarek Olšák2017-03-031-0/+1
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* radeonsi: replace AMDGPU.bfe.* with amdgcn.*bfeMarek Olšák2017-03-031-7/+4
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: move kill intrinsic building into amd/commonMarek Olšák2017-03-032-14/+12
| | | | | | just a cleanup Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: set readnone on reads from read-only memoryMarek Olšák2017-03-031-10/+10
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* radeonsi: replace SI.buffer.load.dword with amdgcn.buffer.loadMarek Olšák2017-03-031-45/+19
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* radeonsi: replace SI.packf16 with amdgcn.cvt.pkrtzMarek Olšák2017-03-031-5/+1
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* radeonsi: remove last use of llvm.SI.resinfoMarek Olšák2017-03-031-48/+49
| | | | and move one function up to reuse the code.
* radeonsi: move image intrinsic building to amd/commonMarek Olšák2017-03-031-92/+62
| | | | Reviewed-by: Dave Airlie <[email protected]>
* ac: replace SI.export with amdgcn.exp.*Marek Olšák2017-03-031-3/+5
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: move llvm.SI.export building to amd/commonMarek Olšák2017-03-031-162/+144
| | | | Reviewed-by: Dave Airlie <[email protected]>
* ac: unify build_type_name_for_intr functionsMarek Olšák2017-03-031-44/+5
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: set unorm=1 for TGSI_TEXTURE_SHADOWRECT as wellMarek Olšák2017-03-031-1/+2
| | | | | | It was harmless, because we also set unorm in the sampler state. Reviewed-by: Dave Airlie <[email protected]>
* tgsi/scan: record load/store/atomic image usageMarek Olšák2017-03-031-1/+3
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: add support for an on-disk shader cacheTimothy Arceri2017-03-031-7/+60
| | | | | | | | | | | | | V2: - when loading from disk cache also binary insert into memory cache. - check that the binary loaded from disk is the correct size. If not delete the cache item and skip loading from cache. V3: - remove unrequired variable Reviewed-by: Grigori Goronzy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* swr: fix crash in swr_update_derived following st/mesa state changesBruce Cherniak2017-03-022-3/+46
| | | | | | | | | | | | | | | | | | | | Recent change to st/mesa state update logic caused major regressions to swr validation code. swr uses the same validation logic (swr_update_derived) for both draw and Clear calls. New st/mesa state update logic results in certain state objects not being set/bound during Clear. This was causing null ptr exceptions. Creation of static dummy state objects allows setting these pointers during Clear validation, without interfering with relevant state validation. Once fixed, new logic also highlighted an error in dirty bit checking for fragment shader and clip validation. (The alternative is to have a simplified validation routine for Clear. Which may do that at some point.) Reviewed-by: Tim Rowley <[email protected]>
* swr: enable clear_texture with util_clear_textureBruce Cherniak2017-03-022-1/+2
| | | | | | Passes corresponding piglit tests. Reviewed-by: Edward O'Callaghan <[email protected]>
* svga: fix crash regression since e027935a795Brian Paul2017-03-022-4/+5
| | | | | | | | | | | | During the first update of the hw_clear_state atoms, we may not yet have a current rasterizer state object. So, svga->curr.rast may be NULL and we crash. Add a few null pointer checks to work around this. Note that these are only needed in the state update functions which are called for 'clear' validation. Reviewed-by: Charmaine Lee <[email protected]>
* svga: s/unsigned/pipe_prim_type/Brian Paul2017-03-024-2/+8
| | | | | | And add some default switch cases to silence compiler warnings. Reviewed-by: Charmaine Lee <[email protected]>
* svga: whitespace fixes in svga_context.hBrian Paul2017-03-021-10/+9
| | | | Trivial.
* svga: whitespace and formatting fixes in svga_stage.cBrian Paul2017-03-021-44/+40
| | | | Trivial.
* gallivm,ac: add function attributes at call sites instead of declarationsMarek Olšák2017-03-012-30/+36
| | | | | | | | | | | | | | | | They can vary at call sites if the intrinsic is NOT a legacy SI intrinsic. We need this to force readnone or inaccessiblememonly on some amdgcn intrinsics. This is only used with LLVM 4.0 and later. Intrinsics only used with LLVM <= 3.9 don't need the LEGACY flag. gallivm and ac code is in the same patch, because splitting would be more complicated with all the LEGACY uses all over the place. v2: don't change the prototype of lp_add_function_attr. Reviewed-by: Jose Fonseca <[email protected]> (v1)
* automake: r600: radeonsi: correctly manage libamd_common.la linkingEmil Velikov2017-02-282-4/+5
| | | | | | | | | | | | | | | | | Since both r600 and radeonsi use code from libamd_common they need to static link it. At the same time, adding a common library to LIB_DEPS is fragile [can lean to multiple symbol definitions] and non-obvious - I had to do a double-take how things work atm. So follow the libradeon.la approach and put common libraries in TARGET_RADEON_COMMON Fixes: 936f5407a7d ("gallium/radeon: Add libamd_common.a to TARGET_LIB_DEPS also for r600") Cc: Timothy Arceri <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Acked-by: Marek Olšák <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Tested-by: Michel Dänzer <[email protected]>
* gallium/radeon: Add libamd_common.a to TARGET_LIB_DEPS also for r600Michel Dänzer2017-02-282-1/+5
| | | | | | | | | | | | | | | | | | Fixes build failure with --enable-opencl --enable-xvmc: make[4]: Entering directory '/home/daenzer/src/mesa-git/mesa/build-amd64/src/gallium/targets/xvmc' CXXLD libXvMCgallium.la ../../../../src/gallium/drivers/r600/.libs/libr600.a(evergreen_compute.o): In function `evergreen_create_compute_state': /home/daenzer/src/mesa-git/mesa/build-amd64/src/gallium/drivers/r600/../../../../../src/gallium/drivers/r600/evergreen_compute.c:254: undefined reference to `ac_elf_read' ../../../../src/gallium/drivers/r600/.libs/libr600.a(evergreen_compute.o): In function `r600_shader_binary_read_config': /home/daenzer/src/mesa-git/mesa/build-amd64/src/gallium/drivers/r600/../../../../../src/gallium/drivers/r600/evergreen_compute.c:189: undefined reference to `ac_shader_binary_config_start' /home/daenzer/src/mesa-git/mesa/build-amd64/src/gallium/drivers/r600/../../../../../src/gallium/drivers/r600/evergreen_compute.c:189: undefined reference to `ac_shader_binary_config_start' collect2: error: ld returned 1 exit status Makefile:760: recipe for target 'libXvMCgallium.la' failed Fixes: dc4c551a345d ("radeon/ac: switch from radeon_elf_read() to ac_elf_read()") Acked-by: Timothy Arceri <[email protected]> Tested-by: Timothy Arceri <[email protected]>
* radeon: remove unused radeon_elf_util.{c,h}Timothy Arceri2017-02-287-256/+0
| | | | | | We now use the shared code in AMD common instead. Reviewed-by: Marek Olšák <[email protected]>
* radeon/ac: switch to ac_shader_binary_config_start()Timothy Arceri2017-02-282-3/+4
| | | | | | | | For radeonsi we could probably switch to ac_shader_binary_read_config(). However the functions have diverged so just share this helper for now. Reviewed-by: Marek Olšák <[email protected]>
* radeon/ac: switch from radeon_elf_read() to ac_elf_read()Timothy Arceri2017-02-284-6/+4
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeon/ac: switch from radeon_shader_binary to ac_shader_binaryTimothy Arceri2017-02-2812-73/+36
| | | | Reviewed-by: Marek Olšák <[email protected]>
* svga: fix MSVC build error after PIPE_CAP_USER_INDEX_BUFFERS removalBrian Paul2017-02-241-1/+1
| | | | | | | Need to specify the zero for the struct initializer. My earlier test of the patch series was with MinGW, not MSVC. Trivial.
* vc4: Lazily emit our FS/VS input loads.Eric Anholt2017-02-244-75/+93
| | | | | | | | | | | | | | | | | | | This reduces register pressure in both types of shaders, by reordering the input loads from the var->data.driver_location order to whatever order they appear first in the NIR shader. These instructions aren't reorderable at our QIR scheduling level because the FS takes two in lockstep to do an interpolation, and the VS takes multiple read instructions in a row to get a whole vec4-level attribute read. shader-db impact: total instructions in shared programs: 76666 -> 76590 (-0.10%) instructions in affected programs: 42945 -> 42869 (-0.18%) total max temps in shared programs: 9395 -> 9208 (-1.99%) max temps in affected programs: 2951 -> 2764 (-6.34%) Some programs get their max temps hurt, depending on the order that the load_input intrinsics appear, because we end up being unable to copy propagate an older VPM read into its only use.
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