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* r600: use build-id when available for disk cacheTimothy Arceri2018-10-031-7/+7
| | | | Reviewed-by: Marek Olšák <[email protected]>
* nouveau: use build-id when available for disk cacheTimothy Arceri2018-10-031-7/+7
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use build-id when available for disk cacheTimothy Arceri2018-10-031-12/+9
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: avoid sending GS_EMIT in shaders without outputsJózef Kucia2018-10-021-3/+6
| | | | | | | | | Fixes GPU hangs. Cc: 18.1 18.2 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107857 Signed-off-by: Józef Kucia <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: initialize ac_gpu_info::name when using SI_FORCE_FAMILYMarek Olšák2018-10-021-0/+1
| | | | | so that it's not NULL when loading radeonsi and a GCN GPU is not present in the system.
* radeonsi: don't set the VS prolog key for the blit VSMarek Olšák2018-10-021-1/+2
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* freedreno/a6xx: hwbinningRob Clark2018-10-028-105/+159
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-10-027-41/+52
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeonsi: add a workaround for bitfield_extract when count is 0Timothy Arceri2018-10-021-11/+30
| | | | | | | | | | | | | | | This ports the fix from 3d41757788ac. Both LLVM 7 & 8 continue to have this problem. It fixes rendering issues in some menu and loading screens of Civ VI which can be seen in the trace from bug 104602. Note: This does not fix the black triangles on Vega for bug 104602. Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104602 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107276
* freedreno/a6xx: Build up draw dword0 outside visibilty if statementKristian H. Kristensen2018-09-271-17/+18
| | | | | | | | Pulling this logic out means we can share the logic and avoid a couple of temporary variables that helped make things clearer before. Note that in either vismode case, we always program vismode 0. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Simplify draw_emit() branches a bitKristian H. Kristensen2018-09-271-16/+8
| | | | | | | | Now that we've copied the emit logic into each branch of the if (info->index_size) statement, we can simplify the logic a bit according to which case we're in. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Copy OUT_RING() part into each branch of the index ifKristian H. Kristensen2018-09-271-17/+29
| | | | Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Split fd6_draw_emit into direct and indirect pathsKristian H. Kristensen2018-09-271-36/+46
| | | | | | | This splits the two code paths into separate functions and moves the "if (info->indirect)" test into draw_impl(). Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Inline fd6_draw()Kristian H. Kristensen2018-09-271-31/+17
| | | | | | Simplify the code a bit by inlining this helper. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Move emit_marker and wfi to draw_impl()Kristian H. Kristensen2018-09-271-17/+12
| | | | | | | This way the markers clearly bracket the draw call and isn't duplicated for both direct and indirect draw code. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Move inline functions out of fd6_draw.hKristian H. Kristensen2018-09-273-108/+110
| | | | | | Only used in fd6_draw.c so put them there. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno: fix a typo in launch_gridHyunjun Ko2018-09-271-1/+1
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* freedreno/ir3: fix the param order of cmpxchgHyunjun Ko2018-09-271-2/+2
| | | | | | | | | | | According to the following definition, int AtomicCompSwap(inout int mem, uint compare, uint data); the preceding one in atomic_comp_swap of NIR is compare and data is followed, while src0 for cmpxchg needs vec2(data, compare) So for ssbo/image deref comp_swap, that should be reversed. Fixes: dEQP-GLES31.functional.image_load_store.*.atomic.comp_swap*
* freedreno/a6xx: fix shaders w/ >= 24 regsRob Clark2018-09-271-1/+1
| | | | | | | | Possibly these bits mean something else now. Blob always seems to use FOUR_QUADS, and changing to TWO_QUADS seems to cause different threads to overlap registers. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: fix gl_FragCoord.wRob Clark2018-09-271-2/+6
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: handle invalidated buffers harderRob Clark2018-09-278-7/+39
| | | | | | Do a better job of skipping mem2gmem/gmem2mem.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: fix constlenRob Clark2018-09-271-7/+6
| | | | | | | | | Fix a few bits of confusion, as with previous gen's constlen is aligned to 4, and value in bitfield is left-shifted by 2 (ie. divided by 4). But this is done by the CONSTLEN() accessor/builder fxn, so don't do it twice. Also HLSQ_FS_CNTL.CONSTLEN is not special. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix inorder rendering caseRob Clark2018-09-271-6/+7
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: backface stencil stateRob Clark2018-09-272-2/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: fix gpu crash with separate-stencilRob Clark2018-09-271-1/+1
| | | | | | | Fixes a crash in (of all things) dEQP-GLES2.info.vendor with --deqp-surface-type=fbo.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: fix MRT configRob Clark2018-09-271-7/+7
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix potential hang when destroying batchRob Clark2018-09-271-1/+1
| | | | | | | batch_flush_reset_dependencies() expects to be called unlocked, and can call fd_batch_reference() which can try to aquire the screen lock again. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix corrupted fb stateRob Clark2018-09-272-2/+5
| | | | | | | | | | | In c3d9f29b we allowed ctx->batch to be null, and started tracking the current framebuffer state in fd_context. But the existing logic in fd_blitter_pipe_begin() would, if !ctx->batch, set null fb state to be restored after blit. Which broke the world of deqp (and probably other things) Fixes: c3d9f29b781 freedreno: allocate ctx's batch on demand Signed-off-by: Rob Clark <[email protected]>
* freedreno: simplify pctx->clear()Rob Clark2018-09-276-74/+11
| | | | | | | | | | | | This is defined to always clear the entire surface(s) specified, regardless of scissor state.. mesa/st will turn scissored clears into a draw. So rip about a bunch of unnecessary machinery. Also remove a comment that was obsolete since using u_blitter to turn clear into draw (for the cases where there isn't a hw blitter fast-path). Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix FD_MESA_DEBUG=flushRob Clark2018-09-272-2/+8
| | | | | | | The logic to force a flush every draw was short-circuited with newer kernels. Also it should apply to clears as well. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix scissor state emitRob Clark2018-09-274-4/+8
| | | | | | | The effective scissor changes based on rasterizer->scissor flag, so we need to re-emit scissor state when rasterizer state changes. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-09-278-340/+1089
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeonsi: NaN should pass kill_ifAxel Davy2018-09-251-1/+2
| | | | | | | | | | | | | | | Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=105333 Fixes: https://github.com/iXit/Mesa-3D/issues/314 For this application, NaN is passed to KILL_IF and is expected to pass. v2: Explain in the code why UGE is used. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]> CC: <[email protected]>
* radeon/uvd: use bitstream coded number for symbols of Huffman tablesLeo Liu2018-09-241-4/+14
| | | | | | | Signed-off-by: Leo Liu <[email protected]> Fixes: 130d1f456(radeon/uvd: reconstruct MJPEG bitstream) Cc: "18.2" <[email protected]> Reviewed-by: Boyuan Zhang <[email protected]>
* nv50/ir: fix link-time build failureRhys Perry2018-09-231-1/+1
| | | | | | | Seems this fixes linking problems that occur in some situations. Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: fix bindless multisampled images on Maxwell+Rhys Perry2018-09-223-5/+45
| | | | | | | | | | | | | | | | | NVC0_CB_AUX_BINDLESS_INFO isn't written to on Maxwell+ and it's too small anyway. With these changes, TXQ is used to determine the number of samples and the coordinate adjustment information looked up in a small array in the driver constant buffer. v2: rework to use TXQ and a small array instead of a larger array with an entry for each texture v3: get rid of the small array and calculate the adjustments in the shader Signed-off-by: Rhys Perry <[email protected]> Fixes: c2ae9b40527 ('nvc0: implement multisampled images on Maxwell+') Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: warn about changing NVC0_CB_AUX_MP_INFO and NVC0_CB_AUX_DRAW_INFORhys Perry2018-09-221-2/+6
| | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: Update counter reading shaders to new NVC0_CB_AUX_MP_INFORhys Perry2018-09-221-18/+18
| | | | | | Fixes: 66ca7e400b8 ('nvc0: add support for programmable sample locations') Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* vc4: Remove dead i == 0 code from the cos() implementation.Eric Anholt2018-09-211-6/+3
| | | | The loop starts at 1.
* vc4: Fix sin(0.0) and cos(0.0) accuracy to fix SDL rendering rotation.Eric Anholt2018-09-211-26/+40
| | | | | | | | | | | | | | | | | | SDL has some shaders that compute sin(angle) and cos(angle) for a rotation matrix in the VS, and angle is usually 0.0. Our previous implementation had quite a bit of error around 0.0, causing single-pixel rotations at typical window sizes. SDL2 has changed as of August 28th (commit 12156:e5a666405750) to not need sin/cos in the VS, but we should still fix this for existing implementations or similar patterns that other programs may have. glsl-cos goes from 32 instructions to 36, but 9 uniforms to 7. glsl-sin goes from 32 instructions to 34, but 8 uniforms to 7. This seems like a fine impact to have for the bugfix. Cc: 18.1 18.2 <[email protected]> Fixes: https://github.com/anholt/mesa/issues/110
* svga: fix uninitialized fields in DefineDepthStencilView/DefineStreamOutputCharmaine Lee2018-09-201-0/+9
| | | | | | | This patch fixes uninitialized fields in DefineDepthStencilView and DefineStreamOutput commands that are not relevant in SM4 device. Reviewed-by: Brian Paul <[email protected]>
* r300g: add PIPE_SHADER_CAP_SCALAR_ISA switch case to silence warningBrian Paul2018-09-201-0/+4
| | | | Reviewed-by: Mathias Fröhlich <[email protected]>
* svga: Enable Opengl 3.3 compatibility profileNeha Bhende2018-09-201-1/+1
| | | | | | | | | | With this patch, svga driver will start advertising OpenGL 3.3 compatibility profile. Tested with some mesa demos, piglit and glretrace. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* svga: Apply texcoord scale factors only if there is sampler viewNeha Bhende2018-09-201-1/+1
| | | | | | | | | | | | | We need to convert unnormalized texcoords to normalized texcoords when we are sampling from texture. We don't need this conversion if there is no sampler view. Tested with piglit, glretrace Fixes vmware bug 2101970 Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* svga: fix texture array layer index in transfer mapCharmaine Lee2018-09-202-66/+42
| | | | | | | | | | | | | | | | | | | | | In gallium, the layer index of a texture array to be mapped is specified in the z component, whereas in svga device, the index is specified in a separate argument. Currently in svga_texture_transfer_map(), we explicitly modify the z value in the base transfer map to 0 so the layer offset will not be applied twice, but this causes problem when state tracker later refers to the base transfer map and expects the slice index to be specified in z (commit 463b0ea1f6762b7e0536cfadc4e384840af3e8e0). To fix the problem, this patch makes a local copy of the box in svga_transfer and modifies the z value in this copy instead. Fixes spec@khr_texture_compression-astc piglit test crashes. Fixes regression in the dma path with commit 1fdd3dd94a. Tested with mtt glretrace, piglit on Windows VM and Linux VM. Reviewed-by: Brian Paul <[email protected]>
* Revert "radeonsi: avoid syncing the driver thread in si_fence_finish"Timothy Arceri2018-09-182-44/+40
| | | | | | | | | | This reverts commit bc65dcab3bc48673ff6180afb036561a4b8b1119. This was manually reverted. Reverting stops the menu hanging in some id tech games such as RAGE and Wolfenstein The New Order. Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107891
* v3d: Switch from FLUSH_ALL_STATE to FLUSH for ending our bin CLs.Eric Anholt2018-09-171-6/+6
| | | | | | The HW for FLUSH_ALL_STATE isn't validated, since the closed driver only uses FLUSH. Now that we don't have any new state at the end of our bin CLs, follow their lead.
* v3d: Stop clearing the OQ state at the end of the job.Eric Anholt2018-09-173-18/+1
| | | | | | Ever since we added OQ support, we've been clearing OQ state at the start of the job anyway. We're intentionally breaking old-and-new-driver-mix systems, because we need to stop using the unvalidated FLUSH_ALL_STATE.
* v3d: Always emit a TF disable at the start of drawing on V3D 4.x.Eric Anholt2018-09-173-10/+8
| | | | | | | | | | The HW's FLUSH_ALL_STATE is not validated, so we probably shouldn't use it, meaning that we need to reset state at the start. By doing this, we also make ourselves more resilient to another client leaving the TF state enabled at the end of their batch (as we now do, ourselves). However, we still need to emit a single TF disable at the end of the frame, for SWVC5-718.
* r600/sb: use safe math optimizations when TGSI contains precise operationsGert Wollny2018-09-153-1/+5
| | | | | | | | | | Fixes: dEQP-GLES3.functional.shaders.invariance.highp.common_subexpression_3 dEQP-GLES3.functional.shaders.invariance.mediump.common_subexpression_3 dEQP-GLES3.functional.shaders.invariance.lowp.common_subexpression_3 Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
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