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* nvc0: collapse output slots to have adjacent registersIlia Mirkin2018-02-271-2/+12
* nvir/gm107: consider FILE_FLAGS dependencies in SchedDataCalculatorGM107Karol Herbst2018-02-261-1/+14
* nvir/gm107: iterate over all defs in SchedDataCalculatorGM107::findFirstUseKarol Herbst2018-02-261-16/+18
* radeonsi: remove 2 unused user SGPRs from merged TES-GS with 32-bit pointersMarek Olšák2018-02-264-11/+35
* radeonsi: make SI_SGPR_VERTEX_BUFFERS the last user SGPR inputMarek Olšák2018-02-264-20/+53
* radeonsi: set correct num_input_sgprs for VS prolog in merged shadersMarek Olšák2018-02-261-24/+24
* radeonsi: allow fewer input SGPRs in 2nd shader of merged shadersMarek Olšák2018-02-261-1/+5
* radeonsi: don't use struct si_descriptors for vertex buffer descriptorsMarek Olšák2018-02-266-33/+46
* r600: fix tgsi clock last settingDave Airlie2018-02-261-0/+1
* r600: add time lo/hi debugging output.Dave Airlie2018-02-262-0/+12
* radeonsi/nir: enable lowering of fpowTimothy Arceri2018-02-261-0/+1
* radeonsi/nir: fix loading of doubles for tess varyingsTimothy Arceri2018-02-261-2/+10
* radeonsi/nir: fix lds store in tcs outputs handlingTimothy Arceri2018-02-261-1/+1
* r600: Take ALU_EXTENDED into account when evaluating jump offsetsGert Wollny2018-02-261-2/+7
* radeonsi: remove si_descriptors parameter from emit_shader_pointer functionsMarek Olšák2018-02-241-12/+13
* radeonsi: preload the tess offchip ring in TESMarek Olšák2018-02-242-12/+10
* radeonsi: move tess ring address into TCS_OUT_LAYOUT, removes 2 TCS user SGPRsMarek Olšák2018-02-245-91/+70
* radeonsi: move 2nd-shader descriptor pointers into s[0:1]Marek Olšák2018-02-243-74/+140
* radeonsi: change si_descriptors::shader_userdata_offset type to shortMarek Olšák2018-02-242-9/+9
* radeonsi: put both tessellation rings into 1 bufferMarek Olšák2018-02-244-29/+18
* radeonsi: move tessellation ring info into si_screenMarek Olšák2018-02-243-45/+52
* radeonsi: move TCS_OUT_LAYOUT.PatchVerticesIn to lower bitsMarek Olšák2018-02-243-5/+6
* nvir: dont optimize mad with subops to shladdKarol Herbst2018-02-241-1/+2
* broadcom/vc5: Fix layout of 3D textures.Eric Anholt2018-02-232-32/+81
* broadcom/vc5: Ignore unused usage flags in is_format_supported.Eric Anholt2018-02-231-27/+16
* swr: remove dead LLVM code pathsEmil Velikov2018-02-233-28/+0
* broadcom/vc4: Remove the retval==usage check in is_format_supported().Eric Anholt2018-02-231-26/+13
* broadcom/vc4: Add support for YUV textures using unaccelerated blits.Eric Anholt2018-02-233-3/+35
* broadcom/vc4: Fix double-unrefcounting of prsc->next with shadows.Eric Anholt2018-02-231-6/+11
* broadcom/vc4: Add pipe_reference debugging for vc4_bos.Eric Anholt2018-02-232-5/+24
* broadcom/vc4: Remove dead vc4_bo_set_reference().Eric Anholt2018-02-231-8/+0
* broadcom/vc4: Use pipe_resource_reference in sampler views.Eric Anholt2018-02-231-2/+2
* broadcom/vc4: Allow importing linear BOs with arbitrary offset/stride.Eric Anholt2018-02-231-8/+25
* broadcom/vc4: Ignore PIPE_BIND_DISPLAY_TARGET in is_format_supported().Eric Anholt2018-02-231-0/+2
* etnaviv: fix in-place resolve tile countLucas Stach2018-02-232-2/+4
* etnaviv: switch magic single buffer state to "3"Lucas Stach2018-02-231-1/+1
* etnaviv: add debug switch to disable single buffer featureLucas Stach2018-02-232-0/+4
* etnaviv: npot_tex_any_wrap needs one bit onlyChristian Gmeiner2018-02-231-1/+1
* nv50,nvc0: fix integer MS resolves using 2d engineIlia Mirkin2018-02-221-1/+2
* nvc0: fix writing query results into bufferIlia Mirkin2018-02-221-4/+10
* nv50,nvc0: fix clear buffer accelerationIlia Mirkin2018-02-222-28/+17
* radeonsi/nir: collect more accurate output_usagemaskTimothy Arceri2018-02-221-13/+43
* radeonsi/nir: disable GLSL IR loop unrollingTimothy Arceri2018-02-221-0/+2
* radeonsi/nir: fix tess varying loads for doublesTimothy Arceri2018-02-221-2/+2
* ac/radeonsi: pass type to load_tess_varyings()Timothy Arceri2018-02-222-0/+3
* radeonsi: don't flush when si_eliminate_fast_color_clear is no-opMarek Olšák2018-02-211-1/+5
* radeonsi: make texture_discard_cmask/eliminate functions non-staticMarek Olšák2018-02-212-11/+13
* radeonsi: enable uvd encode for HEVC mainJames Zhu2018-02-211-1/+3
* radeonsi:create uvd hevc enc entryJames Zhu2018-02-211-3/+12
* radeon/uvd:add uvd hevc enc functionsJames Zhu2018-02-213-0/+383
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