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* freedreno: update generated headersRob Clark2015-04-178-42/+354
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: UBO supportRob Clark2015-04-172-0/+52
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move out helperRob Clark2015-04-172-24/+23
| | | | | | We'll also want it in NIR f/e for implementing UBO support. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: sysvals and UBOsRob Clark2015-04-173-24/+56
| | | | | | | | | | Basically just sync up the cmdstream emit parts to match the changes already done on a3xx. Also, fix scheduling for mem instructions. This is needed on a4xx, and I am a bit surprised it isn't needed for a3xx. Signed-off-by: Rob Clark <[email protected]>
* radeonsi: add a debug option to compile shaders when they're createdMarek Olšák2015-04-163-0/+6
| | | | Tested-by: Tom Stellard <[email protected]>
* radeonsi: remove bogus r600-- tripleEmil Velikov2015-04-161-2/+0
| | | | | | | | | | As mentioned by Michel Dänzer for LLVM >= 3.6 we create the LLVMTargetMachine (with triple amdgcn--), as we setup the radeonsi context. For older LLVM or hardware (r600) the triple is always r600-- and is created at a later stage - radeon_llvm_compile() Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* r600g/sb: Skip empty ALU clause while schedulingGlenn Kennard2015-04-161-0/+3
| | | | | | | | | Fixes assert triggered by ext_transform_feedback-intervening-read output use_gs piglit test. Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* vc4: Don't try to use color load/stores to blit across format changes.Eric Anholt2015-04-151-0/+3
| | | | | | We could potentially support the right combination of 8888 to 565, but the important thing for now is to not mix up our orderings of 8888. Fixes fbo-copyteximage regressions.
* vc4: Don't try to use color load/stores to do depth/stencil blits.Eric Anholt2015-04-151-0/+3
| | | | | Fixes regressions in fbo-generatemipmap-formats on depth/stencil (which does blits to work around baselevel/lastlevel).
* vc4: Update the shadow texture for public textures on every draw.Eric Anholt2015-04-153-7/+20
| | | | | We don't know who else has written to it, so we'd better update it every time. This makes the gears spin in X again.
* vc4: Hook up VC4_DEBUG=perf to some useful printfs.Eric Anholt2015-04-153-1/+16
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* radeon/llvm: Improve codegen for KILL_IFTom Stellard2015-04-141-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than emitting one kill instruction per component of KILL_IF's src reg, we now or the components of the src register together and use the result as a condition for just one kill instruction. shader-db stats (bonaire): 979 shaders Totals: SGPRS: 34872 -> 34848 (-0.07 %) VGPRS: 20696 -> 20676 (-0.10 %) Code Size: 749032 -> 748452 (-0.08 %) bytes LDS: 11 -> 11 (0.00 %) blocks Scratch: 12288 -> 12288 (0.00 %) bytes per wave Totals from affected shaders: SGPRS: 1184 -> 1160 (-2.03 %) VGPRS: 600 -> 580 (-3.33 %) Code Size: 13200 -> 12620 (-4.39 %) bytes LDS: 0 -> 0 (0.00 %) blocks Scratch: 0 -> 0 (0.00 %) bytes per wave Increases: SGPRS: 2 (0.00 %) VGPRS: 0 (0.00 %) Code Size: 0 (0.00 %) LDS: 0 (0.00 %) Scratch: 0 (0.00 %) Decreases: SGPRS: 5 (0.01 %) VGPRS: 5 (0.01 %) Code Size: 25 (0.03 %) LDS: 0 (0.00 %) Scratch: 0 (0.00 %) *** BY PERCENTAGE *** Max Increase: SGPRS: 32 -> 40 (25.00 %) VGPRS: 0 -> 0 (0.00 %) Code Size: 0 -> 0 (0.00 %) bytes LDS: 0 -> 0 (0.00 %) blocks Scratch: 0 -> 0 (0.00 %) bytes per wave Max Decrease: SGPRS: 32 -> 24 (-25.00 %) VGPRS: 16 -> 12 (-25.00 %) Code Size: 116 -> 96 (-17.24 %) bytes LDS: 0 -> 0 (0.00 %) blocks Scratch: 0 -> 0 (0.00 %) bytes per wave *** BY UNIT *** Max Increase: SGPRS: 64 -> 72 (12.50 %) VGPRS: 0 -> 0 (0.00 %) Code Size: 0 -> 0 (0.00 %) bytes LDS: 0 -> 0 (0.00 %) blocks Scratch: 0 -> 0 (0.00 %) bytes per wave Max Decrease: SGPRS: 32 -> 24 (-25.00 %) VGPRS: 16 -> 12 (-25.00 %) Code Size: 424 -> 356 (-16.04 %) bytes LDS: 0 -> 0 (0.00 %) blocks Scratch: 0 -> 0 (0.00 %) bytes per wave Reviewed-by: Marek Olšák <[email protected]>
* radeon/llvm: Run LLVM's instruction combining passTom Stellard2015-04-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This should improve code quality in general and will help with some future changes to how we emit kill instructions. shader-db shows a few regressions, but these don't seem to be the result of deficiencies in instcombine. They're mostly caused by the scheduler making different decisions than before. shader-db stats (bonaire): 979 shaders Totals: SGPRS: 35056 -> 34872 (-0.52 %) VGPRS: 20624 -> 20696 (0.35 %) Code Size: 764372 -> 749032 (-2.01 %) bytes LDS: 11 -> 11 (0.00 %) blocks Scratch: 12288 -> 12288 (0.00 %) bytes per wave Totals from affected shaders: SGPRS: 13264 -> 13072 (-1.45 %) VGPRS: 8248 -> 8316 (0.82 %) Code Size: 486320 -> 470992 (-3.15 %) bytes LDS: 11 -> 11 (0.00 %) blocks Scratch: 11264 -> 11264 (0.00 %) bytes per wave Increases: SGPRS: 6 (0.01 %) VGPRS: 20 (0.02 %) Code Size: 14 (0.01 %) LDS: 0 (0.00 %) Scratch: 0 (0.00 %) Decreases: SGPRS: 32 (0.03 %) VGPRS: 8 (0.01 %) Code Size: 244 (0.25 %) LDS: 0 (0.00 %) Scratch: 0 (0.00 %) *** BY PERCENTAGE *** Max Increase: SGPRS: 32 -> 48 (50.00 %) VGPRS: 12 -> 20 (66.67 %) Code Size: 216 -> 224 (3.70 %) bytes LDS: 0 -> 0 (0.00 %) blocks Scratch: 0 -> 0 (0.00 %) bytes per wave Max Decrease: SGPRS: 40 -> 32 (-20.00 %) VGPRS: 16 -> 12 (-25.00 %) Code Size: 368 -> 280 (-23.91 %) bytes LDS: 0 -> 0 (0.00 %) blocks Scratch: 0 -> 0 (0.00 %) bytes per wave *** BY UNIT *** Max Increase: SGPRS: 32 -> 48 (50.00 %) VGPRS: 28 -> 36 (28.57 %) Code Size: 39320 -> 40132 (2.07 %) bytes LDS: 0 -> 0 (0.00 %) blocks Scratch: 0 -> 0 (0.00 %) bytes per wave Max Decrease: SGPRS: 72 -> 64 (-11.11 %) VGPRS: 48 -> 40 (-16.67 %) Code Size: 6272 -> 5852 (-6.70 %) bytes LDS: 0 -> 0 (0.00 %) blocks Scratch: 0 -> 0 (0.00 %) bytes per wave Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Add header and footer to shader stat dumpTom Stellard2015-04-141-2/+4
| | | | | | This makes it easier to parse. Reviewed-by: Marek Olšák <[email protected]>
* vc4: Add a blitter path using just the render thread.Eric Anholt2015-04-131-0/+127
| | | | | This accelerates the path for generating the shadow tiled texture when asked to sample from a raster texture (typical in glamor).
* vc4: Allow submitting jobs with no bin CL in validation.Eric Anholt2015-04-134-11/+19
| | | | | | For blitting, we want to fire off an RCL-only job. This takes a bit of tweaking in our validation and the simulator support (and corresponding new code in the kernel).
* vc4: Move the blit code to a separate file.Eric Anholt2015-04-134-64/+92
| | | | | There will be other blit code showing up, and it seems like the place you'd look.
* vc4: Separate out a bit of code for submitting jobs to the kernel.Eric Anholt2015-04-134-90/+139
| | | | | | I want to be able to have multiple jobs being set up at the same time (for example, a render job to do a little fixup blit in the course of doing a render to the main FBO).
* vc4: When asked to sample from a raster texture, make a shadow tiled copy.Eric Anholt2015-04-131-2/+9
| | | | | | | | | | | So, it turns out my simulator doesn't *quite* match the hardware. And the errata about raster textures tells you most of what's wrong, but there's still stuff wrong after that. Instead, if we're asked to sample from raster, we'll just blit it to a tiled temporary. Raster textures should only be screen scanout, and word is that it's faster to copy to tiled using the tiling engine first than to texture from an entire raster texture, anyway.
* vc4: Fix off-by-one in branch target validation.Eric Anholt2015-04-131-1/+1
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* vc4: Use NIR-level lowering for idiv.Eric Anholt2015-04-131-11/+1
| | | | This fixes the idiv tests in piglit.
* vc4: Add a bunch of type conversions.Eric Anholt2015-04-131-0/+12
| | | | | | These are required to get piglit's idiv tests working. The unsigned<->float conversions are wrong, but are good enough to get piglit's small ranges of values working.
* vc4: Use the blit interface for updating shadow textures.Eric Anholt2015-04-131-13/+31
| | | | | This lets us plug in a better blit implementation and have it impact the shadow update, too.
* vc4: Remove dead fields from vc4_surface.Eric Anholt2015-04-131-3/+0
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* vc4: Skip sending down the clear colors if not clearing.Eric Anholt2015-04-131-5/+7
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* vc4: Sync with kernel changes to relax BCL versus RCL validation.Eric Anholt2015-04-131-22/+3
| | | | There was no reason to tie the two packets' values together.
* vc4: Fix another space allocation mistake.Eric Anholt2015-04-131-0/+1
| | | | | | We're over-allocating our BCL in vc4_draw.c, so this never mattered. However, new RCL-only blit support might end up here without having set up any BCL contents.
* vc4: Add missed accounting for the size of the semaphore.Eric Anholt2015-04-131-0/+2
| | | | This wouldn't have mattered except in the worst case scenario RCL setup.
* freedreno/ir3/nir: couple little fixesRob Clark2015-04-111-2/+10
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: handle system valuesRob Clark2015-04-111-3/+50
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: handle txs and query_levels tex opsRob Clark2015-04-111-4/+81
| | | | | | | | These correspond to the tgsi TXQ opcode (plus sneak in a fix for two-sided color) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: split out tex helpersRob Clark2015-04-111-34/+72
| | | | | | We'll need these in one or two other spots. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: simplify emit_tex()Rob Clark2015-04-112-61/+66
| | | | | | | | Just build up arrays for src0/src1, and use create_collect().. Also add back missing .3d flag for 3d/cube textures. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/cp: handle indirect properlyRob Clark2015-04-111-13/+20
| | | | | | | | | I noticed some cases where we where trying to copy-propagate indirect src's into places they cannot go, like 2nd src for cat3 (mad, etc). Expand out valid_flags() to be aware of relativ flag, and fix up a few related spots. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/sched: avoid getting stuck on addr conflictsRob Clark2015-04-111-32/+42
| | | | | | | | | | | | | | | | | | When we get in a scenario where we cannot schedule any more instructions due to address register conflict, clone the instruction that writes the address register, and switch the remaining unscheduled users for the current address register over to the new clone. This is simpler and more robust than the previous attempt (which tried and sometimes failed to ensure all other dependencies of users of the address register were scheduled first).. hint it would try to schedule instructions that were not actually needed for any output value. We probably need to do the same with predicate register, although so far it isn't so heavily used so we aren't running into problems with it (yet). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: add variable-indexing supportRob Clark2015-04-111-16/+204
| | | | | | | | A bit fugly.. try and make this cleaner.. note if we hoist all the get_addr() out of the loop we can drop the hashtable and just use create_addr().. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/asm: change assert to warningRob Clark2015-04-111-1/+4
| | | | | | | | It probably *should* be an assert, but for now TGSI f/e isn't very good about dealing w/ CONST vs ABS/NEG. So for debug builds, print a warning instead of crashing with an assert for now. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: set first_driver_paramRob Clark2015-04-111-0/+2
| | | | | | | Without this, a3xx breaks.. a4xx would too if it had already implemented support for passing driver params. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/cp: support to swap mad src'sRob Clark2015-04-114-9/+43
| | | | | | | | | | | | | | | | For a normal MAD (ie. not MADSH), if first source is gpr and second source is const, we can swap the first two sources to avoid needing a mov instruction. This gives back the biggest advantage TGSI f/e had over NIR f/e for common shaders, since TGSI f/e had this logic in the f/e. Note that doing this in copy-prop step has the advantage that it will also work for cases like: MOV TEMP[b], CONST[x] MAD TEMP[d], TEMP[a], TEMP[b], TEMP[c] Signed-off-by: Rob Clark <[email protected]>
* gallivm: don't use control flow when doing indirect constant buffer lookupsRoland Scheidegger2015-04-091-2/+4
| | | | | | | | | | | | | | | | | | | | | | | llvm goes crazy when doing that, using way more memory and time, though there's probably more to it - this points to a very much similar issue as fixed in 8a9f5ecdb116d0449d63f7b94efbfa8b205d826f. In any case I've seen a quite plain looking vertex shader with just ~50 simple tgsi instructions (but with a dozen or so such indirect constant buffer lookups) go from a terribly high ~440ms compile time (consuming 25MB of memory in the process) down to a still awful ~230ms and 13MB with this fix (with llvm 3.3), so there's still obvious improvements possible (but I have no clue why it's so slow...). The resulting shader is most likely also faster (certainly seemed so though I don't have any hard numbers as it may have been influenced by compile times) since generally fetching constants outside the buffer range is most likely an app error (that is we expect all indices to be valid). It is possible this fixes some mysterious vertex shader slowdowns we've seen ever since we are conforming to newer apis at least partially (the main draw loop also has similar looking conditionals which we probably could do without - if not for the fetch at least for the additional elts condition.) v2: use static vars for the fake bufs, minor code cleanups Reviewed-by: Jose Fonseca <[email protected]>
* r600g/sb: Enable SB for geometry shadersGlenn Kennard2015-04-0811-16/+55
| | | | | | | | | | | | | | | | Add SV_GEOMETRY_EMIT special variable type to track the implicit dependencies between CUT/EMIT_VERTEX/MEM_RING instructions so GCM/scheduler doesn't reorder them. Mark emit instructions as unkillable so DCE doesn't eat them. Enable only for evergreen/cayman as there are a few unexplained GS piglit regressions on R6xx/R7xx with SB enabled otherwise. Signed-off-by: Glenn Kennard <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g/sb: Update last_cf for loopsGlenn Kennard2015-04-081-0/+8
| | | | | | | | | | | CF_END could end up emitted in the middle of a shader on cayman when there was a loop at the very end. Fixes glsl-1.50-geometry-end-primitive and ext_transform_feedback-geometry-shaders-basic piglit tests. Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nv50,nvc0: limit the y-tiling of 3d textures to the first level's tilingIlia Mirkin2015-04-063-10/+13
| | | | | | | | | | | | | | We limit y-tiling to 0x20 when depth is involved. However the function is run for each miplevel, and the hardware expects miplevel 0 to have the highest tiling settings. Perform the y-tiling limit on all levels of a 3d texture, not just the ones that have depth. Fixes: texelFetch fs sampler3D 98x129x1-98x129x9 Signed-off-by: Ilia Mirkin <[email protected]> Tested-by: Nick Tenney <[email protected]> # GT216 Cc: "10.4 10.5" <[email protected]>
* r600g: fix op3 abs issueDave Airlie2015-04-071-17/+34
| | | | | | | | | | | This code to handle absolute values on op3 srcs was a bit too simple, it really needs a temp reg per src, not one per channel, make it easier and let sb clean up the mess. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89831 Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* freedreno/ir3: add NIR compilerRob Clark2015-04-057-5/+1762
| | | | | | | | | | | | | | | | The NIR compiler frontend is an alternative to the TGSI f/e, producing the same ir3 IR and using the same backend passes for scheduling, etc. It is not enabled by default yet, as there are still some regressions. To enable, use 'FD_MESA_DEBUG=nir'. It is enough to use with, for example, xonotic or supertuxkart. With the NIR f/e, scalarizing and a number of other lowering steps happen in NIR, so we don't have to do them in ir3. Which simplifies the f/e and allows the lowered instructions to pass through other optimization stages. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: don't decode srgb on mem2gmemIlia Mirkin2015-04-051-6/+12
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: pass sprite coord mode through to program emitIlia Mirkin2015-04-053-1/+4
| | | | | | | | Use the correct sprite replacement depending on the flip of the coord mode, using either T or 1-T depending on whether we have an upper-left or lower-left coordinate origin. This fixes all the point sprite piglits. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add UBO supportIlia Mirkin2015-04-056-38/+132
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: insert nop between sfu/mem operationsIlia Mirkin2015-04-051-1/+6
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno: dirty context when reallocating a bound boIlia Mirkin2015-04-051-0/+40
| | | | Signed-off-by: Ilia Mirkin <[email protected]>