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* freedreno: split out batch clear tracking helperRob Clark2020-06-251-15/+25
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5634>
* freedreno: split out batch draw tracking helperRob Clark2020-06-251-72/+82
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5634>
* freedreno: make foreach_bit() declare it's cursorRob Clark2020-06-255-5/+3
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5634>
* freedreno/ir3: switch PIPE_CAP_TGSI_TEXCOORDRob Clark2020-06-242-6/+9
| | | | | | | | | | | | We don't really need the varying remapping, and it seems to somehow happen twice when shader-cache comes into the picture. But we can just choose not to have this problem. Now that everything is using the ir3_point_sprite() helper, we can flip this pipe cap without it being a massive flag-day. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
* freedreno: convert builtin blit VS prog to ureg builderRob Clark2020-06-241-17/+43
| | | | | | | | | The correct varying semantic to use depends on PIPE_CAP_TGSI_TEXCOORD. To handle this transition switch it over to ureg builder, and query the pipe-cap to choose the appropriate semantic. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
* freedreno/a3xx: use point-coord helperRob Clark2020-06-241-33/+25
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
* freedreno/a4xx: use point-coord helperRob Clark2020-06-241-33/+25
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
* freedreno/a5xx: use point-coord helperRob Clark2020-06-241-33/+25
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
* freedreno/a6xx: use point-coord helperRob Clark2020-06-241-33/+25
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
* freedreno/a6xx: de-duplicate vinterp/vpsrepl state buildingRob Clark2020-06-241-92/+71
| | | | | | | | | | | When we flip the texcoord patch, we'll setup PNTC input slot in the pre-built interp stateobj, rather than this being a draw-time (slow- path) built stateobj. But rather than duplicate more of the slow- path logic, refactor it out into a helper that is reused in both cases. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
* freedreno/ir3: add helper to determine point-coord inputsRob Clark2020-06-241-0/+18
| | | | | | | | | This will simplify a bit the logic for setting up vinterp/vprepl in the driver backend, and also avoid it being a flag-day when we switch the texcoord pipe cap. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
* freedreno/registers: a6xx depth bounds test registersJonathan Marek2020-06-241-2/+2
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5628>
* android: freedreno/ir3: simplify generated sources rulesMauro Rossi2020-06-242-47/+0
| | | | | | | | | | | | | | | Simplification and alignment with meson's sources generation rules Changelog: - move rules from src/gallium/drivers/freedreno/Android.gen.mk to Android.ir3.mk - simplify LOCAL_GENERATED_SOURCES based on $(ir3_GENERATED_FILES) - remove includes of src/gallium/drivers/freedreno/Android.gen.mk - remove src/gallium/drivers/freedreno/Android.gen.mk Signed-off-by: Mauro Rossi <[email protected]> Acked-by: Rob Clark <[email protected]> Acked-by: Eric Engestrom <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5580>
* android: freedreno/ir3: add missing generated sources and rulesMauro Rossi2020-06-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Changelog: - Makefile.sources: add ir3_lexer.c and ir3_parser.{c,h} generated sources - Android.ir3.mk: add the necessary generated sources rules - Android.ir3.mk: add the necessary include paths - src/gallium/drivers/freedreno/Android.gen.mk: generate only ir3_nir_{imul,trig}.c for the moment Fixes the following building error: target C: libfreedreno_ir3 <= external/mesa/src/freedreno/ir3/ir3_assembler.c FAILED: out/target/product/x86_64/obj/STATIC_LIBRARIES/libfreedreno_ir3_intermediates/ir3/ir3_assembler.o ... external/mesa/src/freedreno/ir3/ir3_assembler.c:28:10: fatal error: 'ir3_parser.h' file not found ^~~~~~~~~~~~~~ 1 error generated. Fixes: 1e8808a4a0f ("freedreno/ir3: refactor out helper to compile shader from asm") Signed-off-by: Mauro Rossi <[email protected]> Acked-by: Rob Clark <[email protected]> Acked-by: Eric Engestrom <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5580>
* zink: clamp VkImageCreateInfo.arrayLayers to 1 for image resource creationMike Blumenkrantz2020-06-241-1/+1
| | | | | | | | | this is required by spec, so we can generally assume that any time it's 0 here this is the result of us being lazy elsewhere in the zink driver when we're manually creating this sort of buffer Reviewed-by: Erik Faye-Lund <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5614>
* iris/compute: Split out iris_load_indirect_locationJordan Justen2020-06-241-20/+29
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5571>
* iris: Split walker and state update into iris_upload_gpgpu_walkerJordan Justen2020-06-241-35/+48
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5571>
* freedreno: Handle DRM_FORMAT_MOD_INVALID in shared codeKristian H. Kristensen2020-06-231-0/+6
| | | | | | | | | | | | | | layout_resource_for_modifier() needs to handle DRM_FORMAT_MOD_INVALID as well, since src/gallium/frontends/dri/dri2.c uses this to indicate "no modifier" when it's called through the older non-modifier entry points. This is similar to 334788d4 ("freedreno: allow INVALID modifier") but for the generic implementation. Fixes: 98910626 ("freedreno/a6xx: Implement layout for DRM_FORMAT_MOD_QCOM_COMPRESSED") Closes: #3154 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5611>
* iris: Delete useless #defineKenneth Graunke2020-06-231-1/+0
| | | | | | | | | | When I was bringing up the driver, I had BLORP use #ifdefs for softpin-mode vs. relocation-mode. That all got reworked during review, but apparently this #define is still kicking around, even though nothing uses it. Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5610>
* radeonsi: replace ctx->screen with sscreen in si_flush_gfx_csMarek Olšák2020-06-231-4/+4
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5506>
* radeonsi: don't wait for idle at the end of gfx IBsMarek Olšák2020-06-231-0/+14
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5506>
* radeonsi: compact MRTs to save PS export memory spaceMarek Olšák2020-06-232-20/+36
| | | | | | | | | | | | | | If there are holes between color outputs (e.g. a shader exports MRT1, but not MRT0), we can remove the holes by moving higher MRTs lower. The hardware will remap the MRTs to their correct locations if we remove holes in SPI_SHADER_COL_FORMAT but not CB_SHADER_MASK. This is a performance optimization, but MRTs with holes are pretty rare, so there is most likely no effect on any app. Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5535>
* iris: Make use of devinfo has_aux_map fieldJordan Justen2020-06-221-1/+1
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5572>
* util: rename xmlpool.h to driconf.hEric Engestrom2020-06-221-1/+1
| | | | | | | To make it clearer what it is and does. Signed-off-by: Eric Engestrom <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>
* driconf: drop now unused translation facilityEric Engestrom2020-06-223-3/+3
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>
* zink: use correct define value for reserved slot count in ntvMike Blumenkrantz2020-06-221-1/+1
| | | | | | | this is zero-indexed, so we need to include the zero index in the count Reviewed-by: Erik Faye-Lund <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5592>
* iris/bufmgr: Do not use map_gtt or use set/get_tiling on DG1Rafael Antognolli2020-06-223-11/+37
| | | | | | | | | | | | | | | | | | | | | We are starting to see platforms that don't support the get/set tiling uAPI. (For example, DG1.) Additionally on DG1 we shouldn't be using the map_gtt anymore. Let's add some asserts and make sure we don't take those paths accidentally. Rework: * Jordan: Only apply for DG1, not all gen12 * Rafael: Use has_tiling_uapi * Jordan: Copy has_tiling_uapi from devinfo * Jordan: merge in "iris: Rework iris_bo_import_dmabuf() a little." * Jordan: Continue to call get/set_tiling on modifier path Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* iris/l3: Enable L3 full way allocation when L3 config is NULLJordan Justen2020-06-221-4/+11
| | | | | | | | | | Reworks: * Jordan: Check for cfg == NULL rather than is_dg1 Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* v3d: Disable PIPE_CAP_PRIMITIVE_RESTARTNeil Roberts2020-06-221-1/+0
| | | | | | | | | | | | | The hardware can only support the PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX subset. This will make it stop advertising the NV_primitive_restart extension without breaking GLES 3.0 support. v2: Update features.txt Reviewed-by: Eric Anholt <[email protected]> (v1) Reviewed by: Erik Faye-Lund <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5559>
* gallium: Add pipe cap for primitive restart with fixed indexNeil Roberts2020-06-2217-0/+17
| | | | | | | | | | | | | | | | | | | | Adds PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX which is a subset of the primitive restart cap for when the hardware can only support the fixed indices specified in GLES. The switch statements were automatically modified with this command: find \( \( -name \*.cpp -o -name \*.c \) \! -type l \) \ -exec sed -i -r \ 's/^(\s*case\s+PIPE_CAP_PRIMITIVE_RESTART)\s*:.*$/\0\n\1_FIXED_INDEX:/' \ {} \; v2: Add a note in screen.rst Reviewed-by: Eric Anholt <[email protected]> (v1) Reviewed by: Erik Faye-Lund <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5559>
* nv50/ir/ra: fix memory corruption when spillingKarol Herbst2020-06-221-22/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When doing RA we end up with adding ValueDef references to Values across all over the shader. This is all fine until we remove the Instruction defining those Values, which happens when spilling values. Instead of manipulating the values directly we should just track all merged in defs in a seperate structure and remove stale references when an instruction gets deleted in the spiller. fixes following libasan report: ================================================================= ==612087==ERROR: AddressSanitizer: heap-use-after-free on address 0x6150003ea380 at pc 0x7f1d12142fe9 bp 0x7fffca6fd120 sp 0x7fffca6fd110 READ of size 8 at 0x6150003ea380 thread T0 #0 0x7f1d12142fe8 in nv50_ir::ValueDef::get() const ../src/gallium/drivers/nouveau/codegen/nv50_ir.h:648 #1 0x7f1d12143c02 in nv50_ir::Value::getUniqueInsn() const ../src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h:229 #2 0x7f1d1221530d in nv50_ir::RegAlloc::BuildIntervalsPass::addLiveRange(nv50_ir::Value*, nv50_ir::BasicBlock const*, int) ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:333 #3 0x7f1d1221872e in nv50_ir::RegAlloc::BuildIntervalsPass::visit(nv50_ir::BasicBlock*) ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:686 #4 0x7f1d1215676c in nv50_ir::Pass::doRun(nv50_ir::Function*, bool, bool) ../src/gallium/drivers/nouveau/codegen/nv50_ir_bb.cpp:495 #5 0x7f1d121563ed in nv50_ir::Pass::run(nv50_ir::Function*, bool, bool) ../src/gallium/drivers/nouveau/codegen/nv50_ir_bb.cpp:477 #6 0x7f1d122262b8 in nv50_ir::RegAlloc::execFunc() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1910 #7 0x7f1d122256b0 in nv50_ir::RegAlloc::exec() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1849 #8 0x7f1d12226f1e in nv50_ir::Program::registerAllocation() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1970 #9 0x7f1d1214092a in nv50_ir_generate_code ../src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:1275 #10 0x7f1d1227461b in nvc0_program_translate ../src/gallium/drivers/nouveau/nvc0/nvc0_program.c:634 #11 0x7f1d12294b21 in nvc0_sp_state_create ../src/gallium/drivers/nouveau/nvc0/nvc0_state.c:620 #12 0x7f1d12294d90 in nvc0_fp_state_create ../src/gallium/drivers/nouveau/nvc0/nvc0_state.c:661 #13 0x7f1d12ad4912 in st_create_fp_variant ../src/mesa/state_tracker/st_program.c:1498 #14 0x7f1d12ad4cd5 in st_get_fp_variant ../src/mesa/state_tracker/st_program.c:1525 #15 0x7f1d12ad8252 in st_precompile_shader_variant ../src/mesa/state_tracker/st_program.c:2053 #16 0x7f1d12c9c851 in st_program_string_notify ../src/mesa/state_tracker/st_cb_program.c:185 #17 0x7f1d12d17731 in st_link_tgsi ../src/mesa/state_tracker/st_glsl_to_tgsi.cpp:7441 #18 0x7f1d12cabaf0 in st_link_shader ../src/mesa/state_tracker/st_glsl_to_ir.cpp:175 #19 0x7f1d127c85ca in _mesa_glsl_link_shader ../src/mesa/program/ir_to_mesa.cpp:3186 #20 0x7f1d1252a9f7 in link_program ../src/mesa/main/shaderapi.c:1285 #21 0x7f1d1252a9f7 in link_program_error ../src/mesa/main/shaderapi.c:1384 #22 0x7f1d1252deb3 in _mesa_LinkProgram ../src/mesa/main/shaderapi.c:1876 #23 0x403e13 in main._omp_fn.0 /home/kherbst/git/shader-db/run.c:926 #24 0x7f1d17b8b4b5 in GOMP_parallel (/lib64/libgomp.so.1+0x124b5) #25 0x4029e4 in main /home/kherbst/git/shader-db/run.c:765 #26 0x7f1d179b51a2 in __libc_start_main ../csu/libc-start.c:308 #27 0x402d1d in _start (/home/kherbst/git/shader-db/run+0x402d1d) 0x6150003ea380 is located 0 bytes inside of 504-byte region [0x6150003ea380,0x6150003ea578) freed by thread T0 here: #0 0x7f1d17e5d96f in operator delete(void*) (/usr/lib64/libasan.so.5.0.0+0x11096f) #1 0x7f1d1214ec0f in __gnu_cxx::new_allocator<nv50_ir::ValueDef>::deallocate(nv50_ir::ValueDef*, unsigned long) /usr/include/c++/9/ext/new_allocator.h:128 #2 0x7f1d1214dc00 in std::allocator_traits<std::allocator<nv50_ir::ValueDef> >::deallocate(std::allocator<nv50_ir::ValueDef>&, nv50_ir::ValueDef*, unsigned long) /usr/include/c++/9/bits/alloc_traits.h:470 #3 0x7f1d1214c5fb in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::_M_deallocate_node(nv50_ir::ValueDef*) /usr/include/c++/9/bits/stl_deque.h:624 #4 0x7f1d121498c4 in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::_M_destroy_nodes(nv50_ir::ValueDef**, nv50_ir::ValueDef**) /usr/include/c++/9/bits/stl_deque.h:758 #5 0x7f1d1214704d in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::~_Deque_base() /usr/include/c++/9/bits/stl_deque.h:680 #6 0x7f1d12145371 in std::deque<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::~deque() /usr/include/c++/9/bits/stl_deque.h:1069 #7 0x7f1d1213bc5b in nv50_ir::Instruction::~Instruction() ../src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:615 #8 0x7f1d1213fb2f in nv50_ir::Program::releaseInstruction(nv50_ir::Instruction*) ../src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:1148 #9 0x7f1d122250fb in nv50_ir::SpillCodeInserter::run(std::__cxx11::list<std::pair<nv50_ir::Value*, nv50_ir::Value*>, std::allocator<std::pair<nv50_ir::Value*, nv50_ir::Value*> > > const&) ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1830 #10 0x7f1d12221445 in nv50_ir::GCRA::allocateRegisters(nv50_ir::ArrayList&) ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1541 #11 0x7f1d122262e9 in nv50_ir::RegAlloc::execFunc() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1913 #12 0x7f1d122256b0 in nv50_ir::RegAlloc::exec() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1849 #13 0x7f1d12226f1e in nv50_ir::Program::registerAllocation() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1970 #14 0x7f1d1214092a in nv50_ir_generate_code ../src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:1275 #15 0x7f1d1227461b in nvc0_program_translate ../src/gallium/drivers/nouveau/nvc0/nvc0_program.c:634 #16 0x7f1d12294b21 in nvc0_sp_state_create ../src/gallium/drivers/nouveau/nvc0/nvc0_state.c:620 #17 0x7f1d12294d90 in nvc0_fp_state_create ../src/gallium/drivers/nouveau/nvc0/nvc0_state.c:661 #18 0x7f1d12ad4912 in st_create_fp_variant ../src/mesa/state_tracker/st_program.c:1498 #19 0x7f1d12ad4cd5 in st_get_fp_variant ../src/mesa/state_tracker/st_program.c:1525 #20 0x7f1d12ad8252 in st_precompile_shader_variant ../src/mesa/state_tracker/st_program.c:2053 #21 0x7f1d12c9c851 in st_program_string_notify ../src/mesa/state_tracker/st_cb_program.c:185 #22 0x7f1d12d17731 in st_link_tgsi ../src/mesa/state_tracker/st_glsl_to_tgsi.cpp:7441 #23 0x7f1d12cabaf0 in st_link_shader ../src/mesa/state_tracker/st_glsl_to_ir.cpp:175 #24 0x7f1d127c85ca in _mesa_glsl_link_shader ../src/mesa/program/ir_to_mesa.cpp:3186 #25 0x7f1d1252a9f7 in link_program ../src/mesa/main/shaderapi.c:1285 #26 0x7f1d1252a9f7 in link_program_error ../src/mesa/main/shaderapi.c:1384 #27 0x7f1d1252deb3 in _mesa_LinkProgram ../src/mesa/main/shaderapi.c:1876 #28 0x403e13 in main._omp_fn.0 /home/kherbst/git/shader-db/run.c:926 previously allocated by thread T0 here: #0 0x7f1d17e5c9d7 in operator new(unsigned long) (/usr/lib64/libasan.so.5.0.0+0x10f9d7) #1 0x7f1d1215046f in __gnu_cxx::new_allocator<nv50_ir::ValueDef>::allocate(unsigned long, void const*) /usr/include/c++/9/ext/new_allocator.h:114 #2 0x7f1d1214ebec in std::allocator_traits<std::allocator<nv50_ir::ValueDef> >::allocate(std::allocator<nv50_ir::ValueDef>&, unsigned long) /usr/include/c++/9/bits/alloc_traits.h:444 #3 0x7f1d1214dbd3 in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::_M_allocate_node() /usr/include/c++/9/bits/stl_deque.h:617 #4 0x7f1d1214c464 in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::_M_create_nodes(nv50_ir::ValueDef**, nv50_ir::ValueDef**) (/home/kherbst/local/lib64/dri//nouveau_dri.so+0x829464) #5 0x7f1d121495cd in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::_M_initialize_map(unsigned long) /usr/include/c++/9/bits/stl_deque.h:716 #6 0x7f1d12146f7d in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::_Deque_base() /usr/include/c++/9/bits/stl_deque.h:507 #7 0x7f1d1214518d in std::deque<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::deque() /usr/include/c++/9/bits/stl_deque.h:912 #8 0x7f1d1213b9c9 in nv50_ir::Instruction::Instruction(nv50_ir::Function*, nv50_ir::operation, nv50_ir::DataType) ../src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:605 #9 0x7f1d1224dd44 in nv50_ir::Function::convertToSSA() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ssa.cpp:385 #10 0x7f1d1224d381 in nv50_ir::Program::convertToSSA() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ssa.cpp:310 #11 0x7f1d121407c0 in nv50_ir_generate_code ../src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:1264 #12 0x7f1d1227461b in nvc0_program_translate ../src/gallium/drivers/nouveau/nvc0/nvc0_program.c:634 #13 0x7f1d12294b21 in nvc0_sp_state_create ../src/gallium/drivers/nouveau/nvc0/nvc0_state.c:620 #14 0x7f1d12294d90 in nvc0_fp_state_create ../src/gallium/drivers/nouveau/nvc0/nvc0_state.c:661 #15 0x7f1d12ad4912 in st_create_fp_variant ../src/mesa/state_tracker/st_program.c:1498 #16 0x7f1d12ad4cd5 in st_get_fp_variant ../src/mesa/state_tracker/st_program.c:1525 #17 0x7f1d12ad8252 in st_precompile_shader_variant ../src/mesa/state_tracker/st_program.c:2053 #18 0x7f1d12c9c851 in st_program_string_notify ../src/mesa/state_tracker/st_cb_program.c:185 #19 0x7f1d12d17731 in st_link_tgsi ../src/mesa/state_tracker/st_glsl_to_tgsi.cpp:7441 #20 0x7f1d12cabaf0 in st_link_shader ../src/mesa/state_tracker/st_glsl_to_ir.cpp:175 #21 0x7f1d127c85ca in _mesa_glsl_link_shader ../src/mesa/program/ir_to_mesa.cpp:3186 #22 0x7f1d1252a9f7 in link_program ../src/mesa/main/shaderapi.c:1285 #23 0x7f1d1252a9f7 in link_program_error ../src/mesa/main/shaderapi.c:1384 #24 0x7f1d1252deb3 in _mesa_LinkProgram ../src/mesa/main/shaderapi.c:1876 #25 0x403e13 in main._omp_fn.0 /home/kherbst/git/shader-db/run.c:926 SUMMARY: AddressSanitizer: heap-use-after-free ../src/gallium/drivers/nouveau/codegen/nv50_ir.h:648 in nv50_ir::ValueDef::get() const Shadow bytes around the buggy address: 0x0c2a80075420: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x0c2a80075430: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x0c2a80075440: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x0c2a80075450: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa 0x0c2a80075460: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa =>0x0c2a80075470:[fd]fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd 0x0c2a80075480: fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd 0x0c2a80075490: fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd 0x0c2a800754a0: fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fa 0x0c2a800754b0: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa 0x0c2a800754c0: fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd Shadow byte legend (one shadow byte represents 8 application bytes): Addressable: 00 Partially addressable: 01 02 03 04 05 06 07 Heap left redzone: fa Freed heap region: fd Stack left redzone: f1 Stack mid redzone: f2 Stack right redzone: f3 Stack after return: f5 Stack use after scope: f8 Global redzone: f9 Global init order: f6 Poisoned by user: f7 Container overflow: fc Array cookie: ac Intra object redzone: bb ASan internal: fe Left alloca redzone: ca Right alloca redzone: cb Shadow gap: cc ==612087==ABORTING v2: full rework v3: manage a full copy instead of recreating new lists on every access Closes: #3066 Signed-off-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5277>
* nv50/ir/ra: convert some for loops to Range-based for loopsKarol Herbst2020-06-221-11/+8
| | | | | | | I will touch them in the next commit Signed-off-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5277>
* panfrost: Copy resources when mapping to avoid waiting for readersIcecream952020-06-221-1/+23
| | | | | | | | | | | It is often faster to copy the whole resource and modify that than to flush and wait for readers of the BO. Helps anything which updates textures after already using them in a frame, such as most GLQuake ports. Reviewed-by: Tomeu Vizoso <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5573>
* panfrost: Update sampler views when the texture bo changesIcecream952020-06-223-1/+4
| | | | | | | | | | | The BO reallocation path in panfrost_transfer_map caused textures and sampler views to get out of sync. v2: Use the GPU address of the BO in case two BOs get allocated at the same address. Reviewed-by: Tomeu Vizoso <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5573>
* panfrost: RGBA4 and RGB5_A1 framebuffer supportIcecream952020-06-222-0/+3
| | | | | | | Tested with fbo_firecube. Reviewed-by: Tomeu Vizoso <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5573>
* r600/sfn: Don't set num_components on TESS sysvalue intrinsicsGert Wollny2020-06-222-12/+8
| | | | | | | | | | | | These instructions are not vectorized, and validation rules added for this with 167fa2887f09 nir/validate: validate intr->num_components Fixes: 46a3033b43b9b51cae5c60eea39e7e5af325c4db r600/sfn: Emit some LDS instructions Signed-off-by: Gert Wollny <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5575>
* r600/sfn: Add support for shared atomicsGert Wollny2020-06-226-0/+164
| | | | | Signed-off-by: Gert Wollny <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5575>
* r600/sfn: Add lowering pass for shared IOGert Wollny2020-06-221-0/+90
| | | | | | | Lower shared load and store to use the r600 specific intrinsics. Signed-off-by: Gert Wollny <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5575>
* nv50/ir/nir: rework CFG handlingKarol Herbst2020-06-221-32/+34
| | | | | | | | | Remove all convergency handling as it was broken and get the code to be a bit closer to TGSI. Also removes pointless asserts. Signed-off-by: Karol Herbst <[email protected]> Tested-by: Ben Skeggs <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5512>
* nv50/ir/nir: rework input output handlingKarol Herbst2020-06-221-43/+34
| | | | | | | | | | New code is a bit more structurized and fixes a bunch of int64 and double fails. Also disables lower_to_scalar which gives us nice vectorized inputs and outputs. Signed-off-by: Karol Herbst <[email protected]> Tested-by: Ben Skeggs <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5512>
* nv50/ir/nir: handle clip vertex for tess eval shadersKarol Herbst2020-06-221-0/+1
| | | | | | Signed-off-by: Karol Herbst <[email protected]> Tested-by: Ben Skeggs <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5512>
* nv50/ir/nir: don't emit a restart with set a stream_idKarol Herbst2020-06-221-2/+7
| | | | | | Signed-off-by: Karol Herbst <[email protected]> Tested-by: Ben Skeggs <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5512>
* nvc0: enable spirv caps with nirKarol Herbst2020-06-221-1/+2
| | | | | | | | This enables the SPIR-V GL extensions moving us a step closer to GL 4.6. Signed-off-by: Karol Herbst <[email protected]> Tested-by: Ben Skeggs <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5512>
* nv50/ir/nir: fix nv_viewport_array2Karol Herbst2020-06-221-0/+1
| | | | | | Signed-off-by: Karol Herbst <[email protected]> Tested-by: Ben Skeggs <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5512>
* nv50/ir/nir: fix ext_demote_to_helper_invocationKarol Herbst2020-06-221-1/+5
| | | | | | Signed-off-by: Karol Herbst <[email protected]> Tested-by: Ben Skeggs <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5512>
* nv50/ir/print: add missing VIEWPORT_MASK handlingKarol Herbst2020-06-221-1/+4
| | | | | | | | Also add an STATIC_ASSERT so we catch those issues automatically. Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5512>
* nv50/ir/nir: add workaround for double vertex attribsKarol Herbst2020-06-221-0/+2
| | | | | | | | | Gallium adjusts the vertrix attrib types for doubles, but can run out of bounds this way. As the slot is counted from 0 anyway, just fix it. Signed-off-by: Karol Herbst <[email protected]> Tested-by: Ben Skeggs <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5512>
* gv100/ir: fix OP_TXG for shadow texturesKarol Herbst2020-06-221-2/+9
| | | | | | | | | | | doesn't seem to fix any tests now, but the previous code was obviously incorrect and I still see fails in those CTS tests: KHR-GL46.texture_gather.*depth* Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5576>
* gv100/ir: fix shift loweringKarol Herbst2020-06-222-19/+17
| | | | | | | | Wrap was ignored. Also merge functions to share code. Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5576>
* gv100/ir: fix atom casKarol Herbst2020-06-222-1/+3
| | | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5576>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-12 09:33:46 +0000