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* radeonsi: fix isolines tess factor writes to control ringNicolai Hähnle2016-12-071-4/+12
* radeonsi: Use amdgcn intrinsics for fs interpolationTom Stellard2016-12-071-54/+142
* freedreno/a5xx: fix draw packet size with index bufferRob Clark2016-12-061-1/+1
* freedreno/a5xx: gmem bypass modeRob Clark2016-12-061-0/+72
* freedreno/a5xx: fix emit_string_marker()Rob Clark2016-12-061-1/+4
* freedreno: pitch alignment should match gmem alignmentRob Clark2016-12-065-15/+22
* freedreno/a5xx: more formatsRob Clark2016-12-061-41/+41
* freedreno/a5xx: fix fragfaceRob Clark2016-12-061-2/+4
* freedreno/a5xx: fix fragcoordRob Clark2016-12-061-4/+11
* freedreno: update generated headersRob Clark2016-12-067-20/+129
* freedreno/a5xx: fix alpha testRob Clark2016-12-063-5/+1
* freedreno/a5xx: fix VPC_VAR[n].DISABLE bitsRob Clark2016-12-061-13/+13
* radeon/vce Handle H.264 level 5.2Andy Furniss2016-12-051-1/+2
* swr: mark PIPE_CAP_NATIVE_FENCE_FD unsupportedTim Rowley2016-12-051-0/+1
* swr: include llvm version and vector width in renderer stringTim Rowley2016-12-051-1/+11
* swr: Fix active_queries countBruce Cherniak2016-12-021-6/+7
* swr: Fix type to match parameters of std::max()George Kyriazis2016-12-021-7/+7
* swr: [rasterizer jitter] include cstdarg in builder_misc.cppTim Rowley2016-12-021-1/+2
* freedreno: no-op render when we need a fenceRob Clark2016-12-013-7/+40
* freedreno: native fence fd supportRob Clark2016-12-017-8/+69
* freedreno: some fence cleanupRob Clark2016-12-019-27/+23
* gallium: support for native fence fd'sRob Clark2016-12-0114-0/+16
* vc4: Avoid false scheduling dependencies for LOAD_IMMs.Eric Anholt2016-11-302-0/+9
* vc4: Try to schedule QIR instructions between writing to and reading math.Eric Anholt2016-11-301-0/+22
* vc4: Improve interleaving of texture coordinates vs results.Eric Anholt2016-11-301-3/+3
* vc4: Fix stray "." on no-op MUL packs.Eric Anholt2016-11-301-6/+6
* vc4: Allow merging instructions with SF set where the other writes NOP.Eric Anholt2016-11-301-0/+1
* vc4: In a loop break/continue, jump if everyone has taken the path.Eric Anholt2016-11-301-10/+17
* swr: add streamout buffer offset into pBuffer pointerIlia Mirkin2016-11-301-2/+3
* swr: fix assertion for max number of so targetsIlia Mirkin2016-11-301-1/+1
* swr: properly report max number of SO componentsIlia Mirkin2016-11-301-1/+1
* swr: turn off queries around blitsIlia Mirkin2016-11-301-1/+9
* swr: don't advertise stream pause/resumeIlia Mirkin2016-11-301-1/+1
* swr: fix range computation for instanced client-side arraysIlia Mirkin2016-11-302-24/+52
* swr: [rasterizer memory] assert when trying to convert an unknown formatIlia Mirkin2016-11-301-0/+1
* swr: remove warning about multi-layer surfacesIlia Mirkin2016-11-301-4/+0
* swr: [rasterizer core] don't attempt to load another RTAI when storingIlia Mirkin2016-11-301-1/+1
* radeonsi: apply the double EVENT_WRITE_EOP workaround to VI as wellMarek Olšák2016-12-011-2/+4
* radeonsi: add a tess+GS hang workaround for VI dGPUsMarek Olšák2016-12-011-2/+10
* radeonsi: don't apply the Z export bug workaround to HainanMarek Olšák2016-12-011-2/+3
* radeonsi: apply a tessellation bug workaround for SIMarek Olšák2016-12-011-0/+7
* radeonsi: apply a TC L1 write corruption workaround for SIMarek Olšák2016-12-011-11/+23
* radeonsi: apply a multi-wave workgroup SPI bug workaround to affected CIK chipsMarek Olšák2016-12-014-4/+29
* radeonsi: consolidate max-work-group-size computationMarek Olšák2016-12-011-24/+19
* freedreno/a5xx: fix negative branchesRob Clark2016-11-302-1/+6
* freedreno: fix android build with a5xxRob Clark2016-11-301-0/+1
* freedreno/a5xx: fix discardRob Clark2016-11-301-3/+4
* freedreno/a5xx: initial supportRob Clark2016-11-3033-17/+4470
* freedreno: update generated headersRob Clark2016-11-3010-100/+4125
* freedreno: make gmem tile size alignment configurableRob Clark2016-11-303-8/+17
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