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* radeon/vcn: update quantiser matrices only when requestedIndrajit Das2018-01-161-6/+11
* radeon/uvd: update quantiser matrices only when requestedIndrajit Das2018-01-161-6/+11
* r600/shader: Initialize max_driver_temp_used correctly for the first timeGert Wollny2018-01-151-0/+1
* freedreno/ir3: "soft" depth scheduling for SFU instructionsRob Clark2018-01-141-9/+21
* freedreno/a5xx: work around SWAP vs TILE_MODE constraintRob Clark2018-01-141-0/+20
* freedreno/a5xx: texture tilingRob Clark2018-01-1416-25/+339
* freedreno: update generated headersRob Clark2018-01-146-26/+35
* freedreno: add screen->setup_slices() for tex layoutRob Clark2018-01-143-19/+43
* r300g: remove double assignmentGrazvydas Ignotas2018-01-141-1/+0
* ac: fix build error in si_shaderMauro Rossi2018-01-131-1/+1
* radv/radeonsi/nir: lower 64bit flrpTimothy Arceri2018-01-131-0/+1
* broadcom/vc5: Fix up channel swizzling for textures on 4.x.Eric Anholt2018-01-121-2/+5
* broadcom/vc5: Port the draw-time state emission to V3D 4.1.Eric Anholt2018-01-127-27/+76
* broadcom/vc5: Rename V3D 3.x Flat Shade Action to match v4.x naming.Eric Anholt2018-01-121-5/+5
* broadcom/vc5: Update pixel center setup for V3D 4.x.Eric Anholt2018-01-121-2/+12
* broadcom/vc5: Print the buffer name in simulator overflow checks.Eric Anholt2018-01-121-2/+4
* broadcom/vc5: Update state setup for V3D 4.1.Eric Anholt2018-01-127-14/+206
* broadcom/vc5: Set up depth formats for V3D 4.x.Eric Anholt2018-01-121-1/+12
* broadcom/vc5: Always use the RGBA8 formats for RGBX8.Eric Anholt2018-01-121-3/+7
* broadcom/vc5: Move the formats table to per-V3D-version compile.Eric Anholt2018-01-1212-337/+451
* broadcom/vc5: Use THRSW to enable multi-threaded shaders.Eric Anholt2018-01-121-3/+26
* broadcom/vc5: Port drawing commands to V3D 4.x.Eric Anholt2018-01-129-20/+93
* broadcom/vc5: Enable the driver on V3D 4.1Eric Anholt2018-01-121-1/+1
* broadcom/vc5: Port the simulator to support V3D 4.1Eric Anholt2018-01-129-125/+216
* broadcom/vc5: Port the RCL setup to V3D4.1.Eric Anholt2018-01-127-58/+360
* broadcom/vc5: Fix per-tile extra clear packet.Eric Anholt2018-01-121-1/+1
* broadcom/vc5: Move the TLB loads and stores to helper functions.Eric Anholt2018-01-121-35/+50
* broadcom/vc5: Convert vc5_cl.h to use the V3DX() macros.Eric Anholt2018-01-127-10/+24
* meson: move libsensors dependency to libgalliumDylan Baker2018-01-114-6/+3
* meson: Use dependencies for nirDylan Baker2018-01-114-13/+15
* meson: Use consistent style for testsDylan Baker2018-01-112-2/+6
* meson: Use consistent styleDylan Baker2018-01-111-2/+4
* svga: simplify failure code in emit_rss_vgpu9()Brian Paul2018-01-111-17/+12
* svga: remove unused fail parameter to EMIT_RS(), EMIT_RS_FLOAT()Brian Paul2018-01-111-57/+57
* svga: add assertion in svga_queue_rs()Brian Paul2018-01-111-0/+1
* svga: whitespace/formatting fixes in svga_state_rss.cBrian Paul2018-01-111-79/+75
* ac: add load_patch_vertices_in() to the abiTimothy Arceri2018-01-111-6/+14
* swr: Handle indirect indices in GSGeorge Kyriazis2018-01-101-8/+39
* amd/common: import get_{load,store}_intr_attribs() from RadeonSISamuel Pitoiset2018-01-101-21/+5
* swr/rast: switch win32 jit format to COFFTim Rowley2018-01-101-2/+2
* swr/rast: don't use 32-bit gathers for elements < 32-bits in sizeTim Rowley2018-01-101-1/+60
* swr/rast: autogenerate named structs instead of literal structsTim Rowley2018-01-101-8/+15
* swr/rast: SIMD16 fetch shader jitter cleanupTim Rowley2018-01-101-720/+368
* swr/rast: shuffle header files for msvc pre-compiled header usageTim Rowley2018-01-1010-88/+143
* swr/rast: SIMD16 builder - cleanup naming (simd2 -> simd16)Tim Rowley2018-01-105-233/+239
* r600: don't emit tes samplers/views when tes isn't activeRoland Scheidegger2018-01-102-0/+19
* r600: increase number of UBOs to 15Roland Scheidegger2018-01-103-22/+37
* r600: use GET_BUFFER_RESINFO vtx fetch on eg instead of setting up constsRoland Scheidegger2018-01-104-58/+50
* r600: increase number of ubos by one to 14Roland Scheidegger2018-01-104-4/+9
* r600: set up constants needed for txq for buffers and cube maps with tesRoland Scheidegger2018-01-101-0/+16
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