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* radeonsi: separate out VS prolog key generationMarek Olšák2017-04-281-11/+20
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: separate out VS prolog key printingMarek Olšák2017-04-281-19/+29
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: code shuffling in si_emit_derived_tess_stateMarek Olšák2017-04-281-31/+38
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: separate out TGSI initialization of si_shader_contextMarek Olšák2017-04-283-43/+72
| | | | | | so that we can put multiple different TGSI shaders into one module. Reviewed-by: Nicolai Hähnle <[email protected]>
* nvc0: Enable compute support for PascalBoyan Ding2017-04-273-4/+7
| | | | | | Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nvc0: Add new launch descriptor format for GP100Boyan Ding2017-04-272-34/+197
| | | | | | | | | | v2: Also handle the the new format in indirect dispatch Use compute class check instead of chipset check Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nvc0: Fix index of unk fields in nve4_cp_launch_descBoyan Ding2017-04-271-2/+2
| | | | | | Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nouveau: Fix indentation of maxwell compute class definitionsBoyan Ding2017-04-271-2/+2
| | | | | | Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi/ac: move vertex export remove to common code.Dave Airlie2017-04-273-163/+14
| | | | | | | | | | | This code can be shared by radv, we bump the max to VARYING_SLOT_MAX here, but that shouldn't have too much fallout. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* svga: fix vertex buffer binding issueBrian Paul2017-04-261-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | When we ran Viewperf11's Maya-03 test 3 we saw warnings about flushing the command buffer with mapped buffers. This happened when transitioning from hardware rendering to a 'draw' fallback path. The problem is the util_set_vertex_buffers_count() function doesn't do exactly what we want in svga_hwtnl_vertex_buffers(). In a case such as dst_count=2, dst={bufA, bufB}, count=1 and src={bufC}, when the function returns we'll have dst_count=2 and dst={bufC, bufB}. What we really want is dst_count=1 and dst={bufC, NULL}. As it was, we were telling the svga device that there were two vertex buffers when in fact we really only needed one for the subsequent drawing command. In this particular case, we first did hardware drawing with {bufA, bufB} then we transitioned to the 'draw' module, consuming vertex data from bufA and bufB and writing the new vertex data to bufC. bufA and bufB are mapped for reading when we flush the command buffer but should not be referenced by the command buffer. The above change fixes that. No Piglit regressions. Also tested with Viewperf, Google Earth, Heaven, etc. VMware bug 1842059 Reviewed-by: Charmaine Lee <[email protected]>
* svga: Removed the unused label 'done' in svga_validate_surface_view()Charmaine Lee2017-04-261-1/+0
| | | | Trivial fix
* svga: use the winsys interface to invalidate surfaceCharmaine Lee2017-04-261-5/+1
| | | | | | | | | | Instead of directly sending the InvalidateGBSurface command, this patch uses the invalidate_surface interface. Fixes Linux VM piglit failures including ext_texture_array-gen-mipmap, fbo-generatemipmap-array S3TC_DXT1 Reviewed-by: Brian Paul <[email protected]>
* svga: fix format for screen targetCharmaine Lee2017-04-261-0/+26
| | | | | | | | | | | | | | | | | | | This patch revises the fix in commit 606f13afa31c9f041a68eb22cc32112ce813f944 to properly translate the surface format for screen target. Instead of changing the svga format for PIPE_FORMAT_B5G6R5_UNORM to SVGA3D_R5G6B5 for all texture surfaces, this patch only restricts SVGA3D_R5G6B5 for screen target surfaces. This avoids rendering failures when specify a non-vgpu10 format in a vgpu10 context with software renderer. Fixes piglit failures spec@!opengl 1.1@draw-pixels, spec@!opengl 1.1@teximage-colors gl_r3_g3_b2 spec@!opengl 1.1@texwrap formats Tested Xorg with 16bits depth. Also tested with MTT piglit, MTT glretrace. Reviewed-by: Brian Paul <[email protected]>
* svga: cache the backing surface handle in the texture objectCharmaine Lee2017-04-265-10/+57
| | | | | | | | | | | | | | | | | | CinebenchR15 not only binds the same texture for rendering and sampling, it actually changes the framebuffer buffer attachment very often, causing a lot of backed surface view to be created and a lot of surface copies to be done. This patch caches the backed surface handle in the texture resource and allows the backed surface view to reuse the backed surface handle. With this patch, the number of backed surface view reduces from 1312 to 3. Unfortunately, this does not eliminate all the surface copies. There are still surface copies involved when we switch from original to backed surface handle for rendering. Tested with CinebenchR15, NobelClinicianViewer, Turbine, Lightsmark2008, MTT glretrace, MTT piglit. Reviewed-by: Brian Paul <[email protected]>
* svga: Update the backing resource only if neededCharmaine Lee2017-04-262-3/+14
| | | | | | | | | | | | | | This patch adds a timestamp in svga_surface structure to keep track of when the backing surface is last sync with the original resource. This helps to avoid unnecessary surface copy from the original resource to the backing surface if the original resource has not since been modified. This reduces the amount of surface copy with CinebenchR15. Tested with CinebenchR15, mtt glretrace. Reviewed-by: Brian Paul <[email protected]>
* svga: Set the surface dirty bit for the right surface viewCharmaine Lee2017-04-261-5/+19
| | | | | | | | For VGPU10, we will render to a backed surface view when the same resource is used for rendering and sampling. In this case, we will mark the dirty bit for the backed surface view. Reviewed-by: Brian Paul <[email protected]>
* svga: Move rendertarget view related fields to hw_clear stateCharmaine Lee2017-04-264-17/+18
| | | | | | | | This patch moves the rendertarget view related fields from svga_hw_draw_state to svga_hw_clear_state where all the hw framebuffer related state resides. Reviewed-by: Brian Paul <[email protected]>
* svga: Move setting the rendered_to flags to framebuffer emit timeCharmaine Lee2017-04-262-18/+28
| | | | | | | Instead of setting the rendered_to flags at set time, this patch moves the setting of the flags to framebuffer emit time. Reviewed-by: Brian Paul <[email protected]>
* svga: add const qualifiers on svga_check_sampler_view_resource_collision()Brian Paul2017-04-262-4/+4
| | | | | | We don't change any of the argument objects. Reviewed-by: Charmaine Lee <[email protected]>
* svga: improve surface view debug messagesBrian Paul2017-04-261-4/+5
| | | | | | The old ones were somewhat cryptic. Reviewed-by: Charmaine Lee <[email protected]>
* svga: add DEBUG_SAMPLERSBrian Paul2017-04-263-1/+4
| | | | | | | | The debug output in svga_create_sampler_state() was controlled by DEBUG_VIEWS but that's not consistent with the other debug output for sampler views. Create/use a new debug flag just for this. Reviewed-by: Charmaine Lee <[email protected]>
* svga: fail screen creation if HW version is too oldBrian Paul2017-04-261-0/+7
| | | | | | | | Tested by verifying 3D acceleration works with HWv8 but not earlier. For HWv7 and older we get the GDI Generic renderer. Reviewed-by: Neha Bhende<[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* nv50,nvc0: disable the TGSI merge registers passSamuel Pitoiset2017-04-262-2/+4
| | | | | | | | | | | | | | | | shader-db results on GK106 (Thanks Karol): total instructions in shared programs : 3931608 -> 3929463 (-0.05%) total gprs used in shared programs : 481255 -> 479014 (-0.47%) total local used in shared programs : 27481 -> 27381 (-0.36%) total bytes used in shared programs : 36031256 -> 36011120 (-0.06%) local gpr inst bytes helped 14 1471 1309 1309 hurt 1 88 384 384 Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* radeonsi: disable the TGSI merge registers passSamuel Pitoiset2017-04-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 47109 shaders in 29632 tests Totals: SGPRS: 1917364 -> 1916620 (-0.04 %) VGPRS: 1165802 -> 1165202 (-0.05 %) Spilled SGPRs: 1880 -> 1843 (-1.97 %) Spilled VGPRs: 70 -> 65 (-7.14 %) Private memory VGPRs: 1184 -> 1184 (0.00 %) Scratch size: 1312 -> 1308 (-0.30 %) dwords per thread Code Size: 60211356 -> 60192268 (-0.03 %) bytes LDS: 1077 -> 1077 (0.00 %) blocks Max Waves: 428597 -> 428674 (0.02 %) Wait states: 0 -> 0 (0.00 %) Totals from affected shaders: SGPRS: 238173 -> 237429 (-0.31 %) VGPRS: 149556 -> 148956 (-0.40 %) Spilled SGPRs: 1263 -> 1226 (-2.93 %) Spilled VGPRs: 25 -> 20 (-20.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 20 -> 16 (-20.00 %) dwords per thread Code Size: 10457904 -> 10438816 (-0.18 %) bytes LDS: 50 -> 50 (0.00 %) blocks Max Waves: 41283 -> 41360 (0.19 %) Wait states: 0 -> 0 (0.00 %) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERSSamuel Pitoiset2017-04-2611-0/+15
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use unsynchronized transfers for shader binary uploadsSamuel Pitoiset2017-04-261-1/+2
| | | | | | | | | | | Because the buffer is new, it can't be referenced by any CS. This can save few CPU cycles by skipping the whole PIPE_TRANSFER_UNSYNCHRONIZED if in amdgpu_bo_map(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: turn si_shader_key::mono into a non-unionMarek Olšák2017-04-263-15/+11
| | | | | | | A merged LS-HS shader needs both fix_fetch and inputs_to_copy for compilation. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: adjust ESGS ring buffer size computation on VIMarek Olšák2017-04-261-1/+4
| | | | | Cc: 17.0 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: don't set deprecated field PARTIAL_ES_WAVE_ONMarek Olšák2017-04-261-2/+3
| | | | | Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: set MAX_PRIMGRP_IN_WAVE in the correct registerMarek Olšák2017-04-262-1/+5
| | | | | Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add a workaround for viewing a slice of 3D as a 2D imageMarek Olšák2017-04-261-8/+22
| | | | | Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix 1D array shader imagesMarek Olšák2017-04-261-0/+1
| | | | | Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix most things wrong with shader imagesMarek Olšák2017-04-262-12/+24
| | | | | | | | | | | | There are 2 major hw changes: - The address must always point to the address of level 0. GFX9 tiling modes don't allow binding to a non-0 level. - 3D must always be bound as 3D, because 2D and 3D use entirely different tiling modes, and the texture target determines which set of modes is used. Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix texture buffer objects and image buffers with IDXEN==0Marek Olšák2017-04-261-1/+34
| | | | | Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ddebug: implement get_query_result_resourceMarek Olšák2017-04-251-0/+16
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* trace: don't trace resource_destroyMarek Olšák2017-04-251-7/+4
| | | | | | | due to the lack of pipe_resource wrapping, we can get this call from inside of driver calls, which would try to lock an already-locked mutex. Reviewed-by: Nicolai Hähnle <[email protected]>
* freedreno/a5xx: hack for r8g8b8a8_snormRob Clark2017-04-231-1/+1
| | | | | | | | | Blob won't render to this format, and sampling from it it uses the same fmt value for r8g8b8_snorm and r8g8b8a8_snorm. But this is what is what blocks us from jumping from gl30/gles20 to gl31/gles30. So a hack it is! Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: rgtc formatsRob Clark2017-04-232-8/+12
| | | | Signed-off-by: Rob Clark <[email protected]>
* etnaviv: Supertiled texture support on gc3000Wladimir J. van der Laan2017-04-222-8/+11
| | | | | | | | | | | | | | | | | Support supertiled textures on hardware that has the appropriate feature flag SUPERTILED_TEXTURE. Most of the scaffolding was already in place in etna_layout_multiple: case ETNA_LAYOUT_SUPER_TILED: *paddingX = 64; *paddingY = 64; *halign = TEXTURE_HALIGN_SUPER_TILED; So this is just a matter of allowing it. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: etnaviv_fence: Simplify the return code logicFabio Estevam2017-04-221-4/+2
| | | | | | | The return code can be simplified by using the logical not operator. Signed-off-by: Fabio Estevam <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* freedreno/a5xx: occlusion queryRob Clark2017-04-224-3/+140
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: drop ring arg from _set_stage()Rob Clark2017-04-227-17/+13
| | | | | | | | It is always the draw ring. Except for a5xx queries like time-elapsed, where we will eventually want to emit cmds into both binning and draw rings. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-04-226-12/+25
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: add support for hw accumulating queriesRob Clark2017-04-228-33/+384
| | | | | | | | | | | | | Some queries on a4xx and all queries on a5xx can do result accumulation on CP so we don't need to track per-tile samples. We do still need to handle pausing/resuming while switching batches (in case the query is active over multiple draws which are executed out of order). So introduce new accumulated-query helpers for these sorts of queries, since it doesn't really fit in cleanly with the original query infra- structure. Signed-off-by: Rob Clark <[email protected]>
* freedreno: a bit of query refactorRob Clark2017-04-224-40/+40
| | | | | | | | Move a bit more of the logic shared by all query types (active tracking, etc) into common code. This avoids introducing a 3rd copy of that logic for a5xx. Signed-off-by: Rob Clark <[email protected]>
* freedreno: make hw-query a helperRob Clark2017-04-2213-16/+57
| | | | | | | | | For a5xx (and actually some queries on a4xx) we can accumulate results in the cmdstream, so we don't need this elaborate mechanism of tracking per-tile query results. So make it into vfuncs so generation specific backend can use it when it makes sense. Signed-off-by: Rob Clark <[email protected]>
* nvc0: Add support for setting viewport index/layer from VS/TESIlia Mirkin2017-04-204-7/+27
| | | | | | | | | | | | | This enables support on GM200+ for: - GL_AMD_vertex_shader_layer - GL_AMD_vertex_shader_layer_viewport_index - GL_ARB_shader_viewport_layer_array Signed-off-by: Ilia Mirkin <[email protected]> [lyude: add relnotes/TES cap] Signed-off-by: Lyude <[email protected]> [imirkin: move relnotes to right place, add features.txt] Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0/ir: Only store viewport in scratch register for GPLyude2017-04-201-0/+1
| | | | | | | | | EMIT only applies to geometry shaders. For everything else, we want to export the viewport normally. Signed-off-by: Lyude <[email protected]> Reviewed-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: fold u_trim_pipe_prim call from st/mesa to driversMarek Olšák2017-04-208-0/+38
| | | | | | | Most drivers don't need it and shouldn't need it because it can't be used in some cases (indirect draws, primitive restart, count from streamout). Reviewed-by: Brian Paul <[email protected]>
* swr: simd16 vs workTim Rowley2017-04-191-5/+25
| | | | | | | Build VS with alternating output for the current simd16 fe double-pump of a simd8 shader. Reviewed-by: Bruce Cherniak <[email protected]>
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