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* gallium/radeon: add GPIN driver query groupNicolai Hähnle2016-02-052-3/+87
| | | | | | | | | This group was used by older versions of AMD GPUPerfStudio (via AMD_performance_monitor) to identify the GPU family, and GPUPerfStudio still complains when it isn't available. Reviewed-by: Edward O'Callaghan <[email protected]> Acked-by: Marek Olšák <[email protected]>
* radeonsi: Allow dumping LLVM IR before optimization passesNicolai Hähnle2016-02-053-2/+16
| | | | | | | | | | | | | | Set R600_DEBUG=preoptir to dump the LLVM IR before optimization passes, to allow diagnosing problems caused by optimization passes. Note that in order to compile the resulting IR with llc, you will first have to run at least the mem2reg pass, e.g. opt -mem2reg -S < shader.ll | llc -march=amdgcn -mcpu=bonaire Signed-off-by: Michel Dänzer <[email protected]> (original patch) Signed-off-by: Nicolai Hähnle <[email protected]> (w/ debug flag) Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: emit LLVM `ret void` before radeon_llvm_finalize_moduleNicolai Hähnle2016-02-053-3/+4
| | | | | | | This allows dumping a consumable LLVM module before the initial optimization passes are run. Reviewed-by: Marek Olšák <[email protected]>
* nvc0: avoid negatives in PUSH_SPACE argumentIlia Mirkin2016-02-051-2/+1
| | | | | | | | | | Fixup to commit 03b3eb90d - the number of buffers could be larger than the number of elements, in which case we'd pass a negative argument to PUSH_SPACE, which would be bad. While we're at it, merge it with the other PUSH_SPACE at the top of the function. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nvc0: add some missing PUSH_SPACE'sIlia Mirkin2016-02-051-1/+9
| | | | | | | | nvc0_vbo has explicit push space checking enabled, so we must run PUSH_SPACE by hand. A few spots missed that. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nvc0/ir: fix converting between predicate and gprIlia Mirkin2016-02-053-11/+41
| | | | | | | | | | The spill logic will insert convert ops when moving between files. It seems like the emission logic wasn't quite ready for these converts. Tested on fermi, and visually looked at nvdisasm output for maxwell. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nvc0: add support for ARB_query_buffer_objectIlia Mirkin2016-02-0411-20/+239
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: add PIPE_CAP_QUERY_BUFFER_OBJECTIlia Mirkin2016-02-0413-0/+13
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: implement PK2H and UP2H opcodesMarek Olšák2016-02-042-1/+75
| | | | | | | | | | | Based on a gallivm patch by Ilia Mirkin. +8 piglit regressions due to precision issues (I blame the tests) The benefit is that we'll get v_cvt_f32_f16 and v_cvt_f16_f32 instead of emulation with integer instructions. They are GLSL 4.00 intrinsics. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix Hyper-Z on StoneyMarek Olšák2016-02-041-0/+4
| | | | | Cc: 11.0 11.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* nv50/ir: make sure to fetch all sources before creating instructionIlia Mirkin2016-02-031-5/+8
| | | | | | | | | We must fetch all sources into the instruction stream before generating the instruction that uses them. Otherwise we'll define values after using them, which won't work so well. Signed-off-by: Ilia Mirkin <[email protected]> Tested-by: Samuel Pitoiset <[email protected]>
* nv50: avoid freeing the symbols if they're about to be storedIlia Mirkin2016-02-031-2/+7
| | | | | | | Spotted by Coverity Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/radeon: support PIPE_CAP_SURFACE_REINTERPRET_BLOCKSNicolai Hähnle2016-02-033-5/+25
| | | | | | | | | This is already used internally in si_resource_copy_region for compressed textures, so the only real change here is the adjusted surface size computation. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* gallium: Add PIPE_CAP_SURFACE_REINTERPRET_BLOCKSNicolai Hähnle2016-02-0314-0/+14
| | | | | | | | | | This cap indicates whether pipe->create_surface can reinterpret a texture as a surface with a format of different block width/height (but equal block size). v2: fix whitespace Reviewed-by: Edward O'Callaghan <[email protected]>
* gallium: Add PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLYNicolai Hähnle2016-02-0314-0/+22
| | | | | | | | | This cap indicates that the driver only supports R, RG, RGB and RGBA formats for PIPE_BUFFER sampler views. v2: move into "unsupported features" section for nouveau (Ilia Mirkin) Reviewed-by: Edward O'Callaghan <[email protected]>
* llvmpipe: use scissor_planes_needed helper functionRoland Scheidegger2016-02-033-18/+33
| | | | So it doesn't get out of sync in multiple places.
* radeonsi: rework RB+ for StoneyMarek Olšák2016-02-024-109/+228
| | | | | | | | | | | | | | | This fixes it. States which also need to be taken into account: - SPI color formats - each down-conversion format supports only a limited set of SPI formats - whether MSAA resolving and logic op are enabled These need special handling: - blending - disabled channels Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: rename cb_target_mask state to cb_render_stateMarek Olšák2016-02-025-14/+15
| | | | | | | | and rename a variable in the function. SX_PS_DOWNCONVERT will be emitted here. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: treat intensity render targets exactly like redMarek Olšák2016-02-021-1/+3
| | | | | | | | | The motivation is to simplify the Stoney RB+ code. Intensity is already treated as red except here. No piglit regressions. Reviewed-by: Nicolai Hähnle <[email protected]>
* llvmpipe: drop scissor planes early if the tri is fully inside themRoland Scheidegger2016-02-022-69/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | If the tri is fully inside a scissor edge (or rather, we just use the bounding box of the tri for the comparison), then we can drop these additional scissor "planes" early. We do not even need to allocate space for them in the tri. The math actually appears to be slightly iffy due to bounding boxes being rounded, but it doesn't matter in the end. Those scissor rects are costly - the 4 planes from the scissor are already more expensive to calculate than the 3 planes from the tri itself, and it also prevents us from using the specialized raster code for small tris. This helps openarena performance by about 8% or so. Of course, it helps there that while openarena often enables scissoring (and even moves the scissor rect around) I have not seen a single tri actually hit the scissor rect, ever. v2: drop individual scissor edges, and do it earlier, not even allocating space for them. v3: help the compiler a bit with simpler code, suggested by Brian. Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: minor cleanup of sse2 for calc_fixed_positionRoland Scheidegger2016-02-021-6/+5
| | | | | | Just slightly simpler assembly. Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: use vector loads for (optimized) tri raster funcsRoland Scheidegger2016-02-022-37/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | When we switched to 64bit rasterization, we could no longer use straight aligned loads for loading the plane data. However, what the code actually does for loading 3 planes, is 12 scalar loads + 9 unpacks, and then there's another 8 unpacks for the transpose we need (!). It would be possible to do the (scalar) loads of course already transposed (at least saving the additional unpacks), however instead just use (un)aligned vector loads, and recalculate the eo values, which is much less instructions (note in case of the triangle_32_3_4 case, the eo values are not even used, making the scalar loads + unpacks for them all the more pointless). This drops execution time of the triangle_32_3_4 function considerably, albeit it doesn't really make a measurable difference (for small tris we're essentially limited by vertex throughput in any case), for triangle_32_3_16 it's essentially noise (the loop is more costly than the initial code there). (I'm thinking about just ditching storing the eo values in the plane data, so could switch back to using aligned planes, however right now they are still used in the other raster functions dealing with planes with scalar code. Also not touching the ppc code, might not be that bad there in any case.) Reviewed-by: Brian Paul <[email protected]>
* virgl: reuse screen when fd is already openRob Herring2016-02-022-0/+7
| | | | | | | | | | It is necessary to share the screen between mesa and gralloc to properly ref count resources. This implements a hash lookup on the file description to re-use an already created screen. This is a similar implementation as freedreno and radeon. Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nouveau/video: wrap assertion within #ifndef NDEBUGMauro Rossi2016-02-011-0/+2
| | | | | | | | | | | | The change is necessary to avoid the following building error in android: external/mesa/src/gallium/drivers/nouveau/nouveau_vp3_video_bsp.c: In function 'nouveau_vp3_bsp_next': external/mesa/src/gallium/drivers/nouveau/nouveau_vp3_video_bsp.c:269:14: error: 'bsp_bo' undeclared (first use in this function) assert(bsp_bo->size >= str_bsp->w0[0] + num_bytes[i]); ^ This matches the declaration of the variables in question. Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: get rid of memory stores with nop valuesIlia Mirkin2016-01-301-0/+6
| | | | | | | | | | | | | | | | | | | | This happens especially with exports and varying packing, where the last bits aren't always filled in. We end up trying to do quad-wide stores, which ends up being a lot of register moves that carefully preserve the nop value. Instead don't do the stores. total instructions in shared programs : 6131375 -> 6125267 (-0.10%) total gprs used in shared programs : 910139 -> 895501 (-1.61%) total local used in shared programs : 15328 -> 15328 (0.00%) local gpr inst helped 0 7442 4693 hurt 0 90 2687 Most of the helped/hurt instruction changes are by one or two ops because can no longer do quad-wide stores in all cases. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: fix false global CSE on instructions with multiple defsIlia Mirkin2016-01-301-0/+2
| | | | | | | | | | | | | | | | | | | | | If an instruction has multiple defs, we have to do a lot more checks to make sure that we can move it forward. Among other things, various code likes to do a, b = tex() if () c = a else c = b which means that a single phi node will have results pointing at the same instruction. We obviously can't propagate the tex in this case, but properly accounting for this situation is tricky. Just don't try for instructions with multiple defs. This fixes about 20 shaders in shader-db, including the dolphin efb2ram shader. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nv50,nvc0: fix buffer clearing to respect engine alignment requirementsIlia Mirkin2016-01-302-52/+247
| | | | | | | | | | | | | | | It appears that the nvidia render engine is quite picky when it comes to linear surfaces. It doesn't like non-256-byte aligned offsets, and apparently doesn't even do non-256-byte strides. This makes arb_clear_buffer_object-unaligned pass on both nv50 and nvc0. As a side-effect this also allows RGB32 clears to work via GPU data upload instead of synchronizing the buffer to the CPU (nvc0 only). Signed-off-by: Ilia Mirkin <[email protected]> # tested on GF108, GT215 Tested-by: Nick Sarnie <[email protected]> # GK208 Cc: [email protected]
* freedreno/ir3: ignore clip-vertex varyingRob Clark2016-01-301-1/+4
| | | | | | | | | | | Since we emulate clip-planes, the clip-vertex is used within the VS itself (thanks to nir_lower_clip). So just ignore it as a VS output. Fixes a boatload of piglit tests that were asserting on unknown varying slot. (Also unrelated spelling/typo fix.) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't ignore local varsRob Clark2016-01-301-1/+7
| | | | | | | | | | | With glsl_to_nir we end up with local variables, instead of global, for arrays. Note that we'll eventually have to do something more clever, I think, when we support multiple functions, but that will probably take some work in a few places. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle tex instrs w/ const offsetRob Clark2016-01-301-0/+16
| | | | | | Something we start to see with glsl_to_nir. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: support load_front_face intrinsicRob Clark2016-01-301-2/+14
| | | | | | | With tgsi_to_nir we get this as a normal input with VARYING_SLOT_FACE. But glsl_to_nir plus nir_lower_system_values this becomes an intrinsic. Signed-off-by: Rob Clark <[email protected]>
* freedreno: limit string marker to max packet sizeRob Clark2016-01-301-0/+3
| | | | | | Experimentally derived max size. Signed-off-by: Rob Clark <[email protected]>
* nvc0: avoid crashing when there are holes in vertex array bindingsIlia Mirkin2016-01-291-3/+13
| | | | | | | | | When using the "shared" vertex array configuration strategy, we bind each of the buffers as a separate array. However there can be holes in such vertex buffer lists, so just emit a disable for those. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nvc0: enable atomic counters and ssboIlia Mirkin2016-01-292-2/+6
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: handle new TGSI MEMBAR opcodeIlia Mirkin2016-01-291-0/+8
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: fix atomic compare-and-swap argumentsIlia Mirkin2016-01-293-5/+8
| | | | | | | Teach the emitter that the two registers are sequential, and drop the second arg entirely, in favor of a double-wide first argument. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add support for indirect buffer loadingIlia Mirkin2016-01-292-10/+31
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add SUQ op by reading the info from driver constbufIlia Mirkin2016-01-296-3/+21
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add support for BUFFER accessesIlia Mirkin2016-01-296-11/+147
| | | | | | | This largely leaves the existing image logic alone. When image support is added this will have to be harmonized somehow. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: handle shader buffer memory barrierIlia Mirkin2016-01-291-0/+4
| | | | | | | Issue a MEM_BARRIER. No idea if this is sufficient. As there are no tests for this, it'll have to do for now. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: add state management for shader buffersIlia Mirkin2016-01-295-8/+111
| | | | | | | (address, length) pairs are uploaded to the driver constbuf as well to make these values available to the shaders. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: double per-shader stage driver constants areaIlia Mirkin2016-01-293-15/+15
| | | | | | We need to store a lot more info now with per-buffer address/size. Signed-off-by: Ilia Mirkin <[email protected]>
* trace: add support for set_shader_buffersIlia Mirkin2016-01-293-0/+60
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v1) v1 -> v2: add arg_begin/arg_end around buffer array Reviewed-by: Samuel Pitoiset <[email protected]>
* nv50/ir: optimize mad/fma with third argument 0 to mulKarol Herbst2016-01-281-0/+21
| | | | | | | | | | | | | | | Very modest effect, but it's clearly the right thing to do. total instructions in shared programs : 6131491 -> 6131398 (-0.00%) total gprs used in shared programs : 910157 -> 910131 (-0.00%) total local used in shared programs : 15328 -> 15328 (0.00%) local gpr inst bytes helped 0 55 85 85 hurt 0 26 20 20 Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: run DCE backwardsKarol Herbst2016-01-281-3/+3
| | | | | | | Reduces calls up to 50% Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: optimize shl(shr(a, c), c) to and(a, ~((1 << c) - 1))Karol Herbst2016-01-281-0/+8
| | | | | | | | | | | | | | | Following shader-db results on GK110: total instructions in shared programs : 6141510 -> 6131491 (-0.16%) total gprs used in shared programs : 910187 -> 910157 (-0.00%) total local used in shared programs : 15328 -> 15328 (0.00%) local gpr inst bytes helped 0 18 821 821 hurt 0 0 0 0 Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* radeonsi: Add option for SI schedulerAxel Davy2016-01-283-1/+7
| | | | | | | | | | Add a debug option to select the LLVM SI Machine Scheduler. R600_DEBUG=sisched Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* vc4: Throttle outstanding rendering after submission.Eric Anholt2016-01-271-0/+9
| | | | | | | | | | | Just make sure that after we've submitted, we get to at least 5 (global) submits ago before we go on to do more. Prevents up to seconds of lag with window movement in X with xcompmgr -c. There may be useful tuning to do in the future, but for now this gets us usability. Cc: "11.0 11.1" <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
* vc4: Don't record the seqno of a failed job submit.Eric Anholt2016-01-271-2/+2
| | | | | | | | | On an error return, the returned seqno will probably be unset, so we'd lose track of what we've submitted so far for waiting on in the future. Cc: "11.0 11.1" <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
* nv50/ir: fix memory corruption when spilling and redoing RAKarol Herbst2016-01-261-0/+3
| | | | | | | | | | | When RA fails, and we spill, we have to clean everything up before doing RA again. We were forgetting to reset the hi/lo linked lists - at least the hi list is guaranteed to still have pointers to now-deleted RIG nodes. Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: [email protected]
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