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* radeonsi: don't enable scratch just for SGPR spillsMarek Olšák2016-06-081-2/+17
* Revert "radeonsi: allow direct hw MSAA resolve for scanout surfaces"Marek Olšák2016-06-081-0/+1
* radeonsi: re-enable PBO ReadPixels accelerationMarek Olšák2016-06-081-3/+6
* radeonsi: allow MSAA resolving into a texture that has DCC enabledMarek Olšák2016-06-082-4/+23
* gallium/radeon: move DCC clearing into a separate functionMarek Olšák2016-06-082-5/+19
* radeonsi: allow direct hw MSAA resolve for scanout surfacesMarek Olšák2016-06-081-1/+0
* radeonsi: don't allocate DCC for the temporary MSAA resolve surfaceMarek Olšák2016-06-083-2/+5
* radeonsi: don't enable DCC in the sampler if first_level doesn't have itMarek Olšák2016-06-083-7/+21
* winsys/amdgpu: enable DCC for mipmapped texturesMarek Olšák2016-06-082-3/+8
* gallium/radeon: don't disable DCC because of SDMAMarek Olšák2016-06-081-20/+3
* radeonsi: don't flag renderbuffer feedback loop if DCC has just been disabledMarek Olšák2016-06-081-2/+4
* radeonsi: add per-level dcc_enabled flagsMarek Olšák2016-06-085-8/+17
* radeonsi: compute DCC register parameters in si_emit_framebuffer_stateMarek Olšák2016-06-084-14/+12
* gallium/radeon: add an assertion checking the validity of PIPE_BIND_SCANOUTMarek Olšák2016-06-081-3/+10
* gallium/radeon: don't allocate DCC for non-renderable texture formatsMarek Olšák2016-06-082-0/+6
* radeonsi: enable WQM in PS prolog when neededNicolai Hähnle2016-06-072-0/+10
* swr: fix provoking vertexTim Rowley2016-06-077-12/+77
* gk104/ir: fix conditions for adding a texbarIlia Mirkin2016-06-071-4/+6
* radeonsi: keep track of dirty descriptor setsNicolai Hähnle2016-06-072-4/+36
* radeonsi: move si_descriptors into a per-context arrayNicolai Hähnle2016-06-073-83/+166
* radeonsi: pass shader stage to si_disable_shader_imageNicolai Hähnle2016-06-071-4/+8
* radeonsi: access descriptor sets via local variablesNicolai Hähnle2016-06-071-31/+41
* radeonsi: add si_set_rw_buffer to be used for internal descriptorsNicolai Hähnle2016-06-073-14/+15
* radeonsi: pass shader stage to si_set_shader_imageNicolai Hähnle2016-06-071-5/+5
* radeonsi: pass shader stage to si_set_sampler_viewNicolai Hähnle2016-06-071-4/+5
* radeonsi: move descriptor set begin_new_cs handling into a separate functionNicolai Hähnle2016-06-071-21/+15
* radeonsi: move enabled_mask out of si_descriptorsNicolai Hähnle2016-06-074-30/+34
* gallium/radeon: add support for sharing textures with DCC between processesMarek Olšák2016-06-073-4/+51
* gallium/radeon: don't discard DCC if an external user can write to itMarek Olšák2016-06-073-12/+31
* i915: fix typo CAP.Dave Airlie2016-06-071-1/+1
* nvc0: add support for VOTE tgsi opcodesIlia Mirkin2016-06-065-24/+77
* gallium: add PIPE_CAP_TGSI_VOTE for when the VOTE ops are allowedIlia Mirkin2016-06-0615-0/+15
* nv50/ir: use round toward 0 when converting doubles to integersSamuel Pitoiset2016-06-061-1/+3
* gallium/radeon: don't re-set BO metadata after CMASK deallocationMarek Olšák2016-06-061-1/+0
* radeonsi: add a performance tweak for 4 SE partsMarek Olšák2016-06-061-0/+11
* radeonsi: simplify PRIMGROUP_SIZE computation for tessellationMarek Olšák2016-06-061-9/+1
* r600g: use hw MSAA resolve for non-trivial resolvesMarek Olšák2016-06-061-9/+53
* radeonsi: use hw MSAA resolve for non-trivial resolvesMarek Olšák2016-06-061-10/+54
* radeonsi: set descriptor dirty mask on shader buffer unbindNicolai Hähnle2016-06-061-0/+1
* svga: print shader linkage info when tgsi debug bit is onCharmaine Lee2016-06-061-2/+5
* nv50,nvc0: fix BGR10_A2UI vertex formatIlia Mirkin2016-06-051-1/+1
* nvc0: do not clear surfaces bins in the validate functionSamuel Pitoiset2016-06-052-5/+2
* nvc0: re-validate images after launching a grid on FermiSamuel Pitoiset2016-06-051-0/+3
* radeonsi: fix images with level > 0Marek Olšák2016-06-051-1/+1
* nvc0: reduce overhead from always marking images dirtyIlia Mirkin2016-06-041-9/+36
* nvc0: reduce overhead from always marking buffers dirtyIlia Mirkin2016-06-041-6/+20
* nvc0: fix memory barrier flag handlingIlia Mirkin2016-06-041-9/+16
* nvc0: mark bound buffer range validIlia Mirkin2016-06-043-0/+9
* gallium/radeon: don't use the DMA ring for pipelined buffer uploadsMarek Olšák2016-06-041-5/+4
* r600g: don't flush caches when binding shader resourcesMarek Olšák2016-06-044-31/+26
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