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* radeon/llvm: Don't lower RETURN to S_ENDPGM on SITom Stellard2012-06-062-1/+4
| | | | | Instead create an S_ENDPGM instruction in the CodeEmitter and emit it after all the other instructions.
* radeon/llvm: Remove AMDIL VCREATE* instructionsTom Stellard2012-06-068-97/+12
| | | | This obsoletes the AMDGPULowerInstruction pass.
* radeon/llvm: Remove AMDIL LOADCONST* instructionsTom Stellard2012-06-0613-322/+33
| | | | This obsoletes the R600LowerInstruction and SIPropagateImmReads passes.
* nouveau: fix scratch buffer leakMarcin Slusarz2012-06-054-3/+15
| | | | ...and create common function for destroying nouveau_context
* nv50: fix nv50_stream_output_state leakMarcin Slusarz2012-06-051-0/+3
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* nv50: fix symbol table memory leakMarcin Slusarz2012-06-051-0/+3
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* radeon/llvm: Fix VTX_READ patternsTom Stellard2012-06-013-4/+33
| | | | | | | | | The VTX_READ instructions were using the ADDRParam ComplexPattern which allows a load instruction's offset to be a register, but VTX_READ instructions can only handle an immediate offset. Also, the load_param pattern fragment had an erroneous return true; statement that was causing it to match the wrong load instructions.
* radeon/llvm: Emit 2 bytes for vertex fetch offsetsTom Stellard2012-06-012-1/+3
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* radeon/llvm: Only use indirect (vertex fetch) parameters for kernelsTom Stellard2012-06-011-2/+6
| | | | | | Kernel parameters can only be retrieved via vertex fetchs. Direct parameters (i.e parameters stored in the constant buffer) are not supported yet.
* radeon/llvm: Eliminate CFGStructurizer dependency on AMDIL instructionsTom Stellard2012-06-0111-41/+124
| | | | | | Add some hooks to the R600,SI InstrInfo and RegisterInfo classes, so that the CFGStructurizer pass can run without any relying on AMDIL instructions.
* radeon/llvm: Change prefix on tablegen files to AMDGPUTom Stellard2012-06-0117-50/+50
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* radeon/llvm: Remove deadcode from the R600LowerInstructions passTom Stellard2012-06-011-46/+2
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* radeon/llvm: Remove AMDIL GLOBALSTORE* instructionsTom Stellard2012-06-014-77/+36
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* radeon/llvm: Remove AMDIL GLOBALLOAD* instructionsTom Stellard2012-06-016-128/+24
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* r600g: compute support for evergreenAdam Rak2012-06-0120-12/+2674
| | | | | | | | | Tom Stellard: - Updated for gallium interface changes - Fixed a few bugs: + Set the loop counter + Calculate the correct number of pipes - Added hooks into the LLVM compiler
* svga: fix saturated TEX instructionsBrian Paul2012-05-311-6/+13
| | | | | | | TEX instructions can't do saturation. Do the TEX into a temp reg w/out saturation, then do a MOV_SAT. Reviewed-by: Jakob Bornecrantz <[email protected]>
* draw: simplify index buffer specificationBrian Paul2012-05-319-28/+28
| | | | | Replace draw_set_index_buffer() and draw_set_mapped_index_buffer() with draw_set_indexes() which simply takes a pointer and an index size.
* nv50: hook up forgotten short constant buffer upload methodMarcin Slusarz2012-05-291-0/+1
| | | | Fixes crash in xorg st.
* radeon/llvm: Update and fix some commentsTom Stellard2012-05-292-12/+6
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* radeonsi: Remove use.sgpr* intrinsics, use load instructions insteadTom Stellard2012-05-295-74/+57
| | | | | | | | | | We now model loading uses sgpr values with LLVM IR load instructions that use the USER_SGPR address space. The definition of the sgpr parameter to the use_sgpr() helper function in radeonsi_shader.c has changed so that you can pass raw sgpr values rather than having to divide the sgpr value you want to use by the dword width of the type you want to load.
* radeonsi: Handle TGSI CONST registersTom Stellard2012-05-2912-100/+254
| | | | | We now emit LLVM load instructions for TGSI CONST register reads, which are lowered in the backend to S_LOAD_DWORD* instructions.
* radeon/llvm: Remove AMDILIntrinsicInfo::GetDeclaration fuction bodyTom Stellard2012-05-291-20/+1
| | | | | | | This function was causing compile errors in the tablegen'd code for some intrinsic definitions. I don't think we really need this function, so I'm removing the function body just as a temporary solution. I'll look into removing the entire AMDILIntrinsicInfo class later.
* radeon/llvm: Remove AMDILTargetMachineTom Stellard2012-05-2919-363/+90
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* nouveau: unreference fences on resource destructionChristoph Bumiller2012-05-292-0/+6
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* nvc0: optimize blend cso by checking which by-RT data actually differsChristoph Bumiller2012-05-291-65/+94
| | | | Can save about 200 bytes of command buffer space.
* nvc0: don't upload UCPs if the shader doesn't use themChristoph Bumiller2012-05-291-1/+1
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* nvc0/ir: allow 64-bit constant loads on nve4Christoph Bumiller2012-05-292-1/+3
| | | | Looks like only 128-bit access doesn't work.
* nvc0/ir: fix texture barrier insertion to prevent WAW hazardsChristoph Bumiller2012-05-296-29/+88
| | | | Fixes, for instance, object highlighting in Diablo 3 (wine).
* nvc0/ir: TEX doesn't support JOIN modifier eitherChristoph Bumiller2012-05-291-0/+1
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* nv30: Fix generic passing to fragment program in NV34.Roy Spliet2012-05-253-5/+9
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* nv30: handle user index buffersChristoph Bumiller2012-05-254-17/+27
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* radeon/llvm: Use a custom inserter for MASK_WRITETom Stellard2012-05-254-34/+36
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* radeon/llvm: Use tablegen pattern to lower bitconvertTom Stellard2012-05-254-294/+11
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* radeon/llvm: Use a custom inserter to lower FNEGTom Stellard2012-05-255-22/+15
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* radeon/llvm: Use a custom inserter to lower CLAMPTom Stellard2012-05-259-84/+41
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* radeon/llvm: Use a custom inserter to lower FABSTom Stellard2012-05-2510-42/+41
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* r600g: handle R16G16B16_FLOAT and R32G32B32_FLOAT in translate_colorswapKai Wasserbäch2012-05-251-0/+2
| | | | | | Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50318 Signed-off-by: Kai Wasserbäch <[email protected]>
* svga: remove the special zero-stride vertex array codeBrian Paul2012-05-259-153/+12
| | | | | This code actually hasn't been needed for some time now. We can just treat a zero-stride vertex array like any other non-zero-stride array.
* Revert "r600g: set round_mode to truncate and get rid of tgsi_f2i on evergreen"Vadim Girlin2012-05-252-6/+56
| | | | | | | | | | | | This reverts commit 60bf0f05b472e66bf1175fcec7a274dab6f7e2a3. It seems round_mode behaves differently in some cases depending on the instruction/slot. Reverting it for now. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50232 Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: add FLT_TO_UINT, UINT_TO_FLT instructionsVadim Girlin2012-05-251-0/+20
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: prepare to revert the round mode state to defaultVadim Girlin2012-05-251-2/+9
| | | | | | | Use TRUNC before FLT_TO_INT on evergreen/cayman. Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: fix sampler index in llvm_emit_texVadim Girlin2012-05-251-2/+4
| | | | | | | | | | Sampler index isn't a second source operand for some tgsi texture instructions. Let's assume it's always the last. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50230 Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: fix opcode for RECIP_UINT_r600Vadim Girlin2012-05-251-1/+1
| | | | | | | | Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50312 Signed-off-by: Vadim Girlin <[email protected]> Tested-by: Kai Wasserbäch <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm/loader: convert hardcoded gpu name to optionVadim Girlin2012-05-251-2/+3
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g: add RECIP_INT, PRED_SETE_INT to r600_bytecode_get_num_operandsVadim Girlin2012-05-251-0/+2
| | | | | | | | Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50315 Signed-off-by: Vadim Girlin <[email protected]> Tested-by: Kai Wasserbäch <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* i915g: Check for geometry shader earlier in i915_set_constant_buffer.Vinson Lee2012-05-241-4/+4
| | | | | | | Fix resource leak defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radeon/llvm: Lower UDIV using the Selection DAGTom Stellard2012-05-248-212/+126
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* radeon/llvm: Remove auto-generated AMDIL->ISA conversion codeTom Stellard2012-05-2414-280/+28
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* radeon/llvm: Remove AMDIL instructions MULHI, SMULTom Stellard2012-05-243-10/+5
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* radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR)Tom Stellard2012-05-248-693/+6
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