summaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers
Commit message (Collapse)AuthorAgeFilesLines
* gm107/ir: fix indirect txq emissionIlia Mirkin2015-07-181-2/+8
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nvc0/ir: don't worry about sampler in txq handlingIlia Mirkin2015-07-181-22/+8
| | | | | | | | | There's no need to deal with samplers for texture size queries. That code also was accidentally setting an invalid sIndirectSrc position, but it can now just be removed. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nvc0/ir: fix txq on indirect samplersIlia Mirkin2015-07-182-2/+56
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* vc4: Switch to using a separate ioctl for making shaders.Eric Anholt2015-07-174-12/+78
| | | | | | | | | This gives the kernel a chance to validate and lock down the data, without having to deal with mmap zapping. With this, GLBenchmark stops on a texture relocations, because we'd recycled a shader BO as another shader and failed to revalidate, since we weren't clearing the cached validation state on mmap faults.
* vc4: Fix printing of shader-db debug when shader-db isn't turned on.Eric Anholt2015-07-171-4/+6
|
* vc4: Add debugging on texture relocation validation failures.Eric Anholt2015-07-171-7/+13
|
* vc4: Also consider uniform 0 in uniform lowering.Eric Anholt2015-07-171-3/+3
| | | | The hash table considers key 0 to be the empty key.
* vc4: Use the pure/const attributes on a bunch of our QPU functions.Eric Anholt2015-07-172-18/+18
| | | | | | On a release build, this makes the rest of vc4_qpu_validate.c go away (the compiler didn't know that our qpu helper function calls had no side effects).
* gallium: add interface for writable shader imagesMarek Olšák2015-07-162-8/+12
| | | | | | PIPE_CAPs will be added some other time. Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: add new limits for shader buffers and imagesMarek Olšák2015-07-161-1/+1
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: add BIND flags for R/W buffers and imagesMarek Olšák2015-07-164-4/+6
| | | | | | | | | | | | | | | | | PIPE_CAPs and TGSI support will be added later. The TGSI support should be straightforward. We only need to split TGSI_FILE_RESOURCE into TGSI_FILE_IMAGE and TGSI_FILE_BUFFER, though duplicating all opcodes shouldn't be necessary. The idea is: * ARB_shader_image_load_store should use set_shader_images. * ARB_shader_storage_buffer_object should use set_shader_buffers(slots 0..M-1) if M shader storage buffers are supported. * ARB_shader_atomic_counters should use set_shader_buffers(slots M..N) if N-M+1 atomic counter buffers are supported. PIPE_CAPs can describe various constraints for early DX11 hardware. Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: add PIPE_CAP_MAX_SHADER_PATCH_VARYINGSMarek Olšák2015-07-1613-0/+13
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* vc4: Cache the texture p1 for the sampler.Eric Anholt2015-07-143-49/+69
| | | | | Cuts another 12% of vc4_uniforms.o, in exchange for computing it at CSO creation time.
* vc4: Cache texture p0/p1 setup for the sampler view.Eric Anholt2015-07-143-28/+43
| | | | | In exchange for a bit of space and computation in CSO setup, we cut vc4_uniform.c (draw time) code size by 4.8%.
* vc4: Move uniforms handling to a separate file.Eric Anholt2015-07-143-314/+341
| | | | | The rest of vc4_program.c is about compiling, while this is about uniform emit at draw time.
* vc4: Fix some -Wdouble-promotion warnings.Eric Anholt2015-07-143-6/+6
| | | | | No code generation changes from this, but it'll be useful to have this next time I go checking -Wdouble-promotion.
* vc4: Fix compiler warnings on release builds.Eric Anholt2015-07-144-7/+14
|
* vc4: Add better debug for register allocation failure.Eric Anholt2015-07-141-1/+5
|
* vc4: Drop reloc_count tracking for debug asserts on non-debug builds.Eric Anholt2015-07-141-0/+10
| | | | Cuts another 88 bytes of compiled code.
* vc4: Rework cl handling to be friendlier to the compiler.Eric Anholt2015-07-146-152/+203
| | | | | Drops 680 bytes of code, from avoiding a bunch of extra updates to the next pointer in the struct.
* vc4: Make a helper function for getting the current offset in the CL.Eric Anholt2015-07-144-20/+21
| | | | | | I needed to rewrite this a bit for safety checking in the next commit. Despite being a static inline of the same thing that was being done, we lose 36 bytes of code for some reason.
* vc4: Drop separate cl*_reloc_hindex().Eric Anholt2015-07-141-18/+6
| | | | | | Now that RCL generation is in the kernel, we don't have any other callers. Oddly, the compiler generates another 8 bytes of code for this, but the simplification is worth it.
* vc4: Store reloc pointers as pointers, not offsets.Eric Anholt2015-07-141-5/+5
| | | | | | | Now that we don't resize the CL as we build (it's set up at the top by vc4_start_draw()), we can store the pointers instead of offsets from the base. Saves a bit of math in emitting relocs (about 60 bytes of code).
* vc4: Add perf debug for when we wait on BOs.Eric Anholt2015-07-144-43/+72
|
* radeonsi: directly include radeon/* headersEmil Velikov2015-07-131-1/+1
| | | | Signed-off-by: Emil Velikov <[email protected]>
* radeonsi: direct emit intrinsic for DFRAC.Dave Airlie2015-07-131-0/+1
| | | | | | Michel reported this still failed, and this fixed it Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: ARB_gpu_shader_fp64 + ARB_vertex_attrib_64bit support.Dave Airlie2015-07-124-11/+171
| | | | | | | | | | | | This adds the translation from TGSI to AMDGPU llvm backend, for the 64-bit opcodes. The backend pretty much handles everything for us fine. There is one patch required for SI DFRAC support, that I know off. [airlied: fixed missing comma, updated relnotes] Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: move sampler/ubo index registers before temp regDave Airlie2015-07-111-7/+6
| | | | | | | | | | | temp_reg needs to be last, as we increment things away from it, otherwise on cayman some tests were overwriting the index regs. Fixes 2 piglit with ARB_gpu_shader5 forced on cayman. Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix sampler/ubo indexing on caymanDave Airlie2015-07-112-6/+18
| | | | | | | | | | Cayman needs a different method to upload the CF IDX0/1 This fixes 31 piglits when ARB_gpu_shader5 is forced on with cayman. Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nv50, nvc0: enable at least one color RT if alphatest is enabledIlia Mirkin2015-07-102-0/+36
| | | | | | | | | Fixes the following piglits: fbo-alphatest-nocolor fbo-alphatest-nocolor-ff Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* freedreno/a4xx: occlusion query supportRob Clark2015-07-101-1/+85
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2015-07-1011-57/+116
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/sched: fixup new instr's blockRob Clark2015-07-101-0/+4
| | | | | | | | | | | | If we split addr/pred, the original instruction could have originated from a different block. If we don't fixup the block ptr we hit asserts later (in debug builds). NOTE: perhaps we don't want to try to preserve addr/pred reg's across block boundaries.. this at least needs some thought in case addr/pred writes end up inside a conditional block.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/ra: fix failed assert for a0/p0Rob Clark2015-07-101-0/+5
| | | | | | | | The address and predicate register are special, they don't get assigned in RA. So do a better job of ignoring them rather than hitting later asserts. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: shader-db tracesRob Clark2015-07-107-8/+67
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix crash in fd_invalidate_resource()Rob Clark2015-07-101-2/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* vc4: unref old fenceRob Clark2015-07-101-0/+2
| | | | | | | | | Some, but not all, state trackers will explicitly unref (and set to NULL) the previous *fence before calling pipe->flush(). So driver should use fence_ref() which will unref the old fence if not NULL. Signed-off-by: Rob Clark <[email protected]> Acked-by: Eric Anholt <[email protected]>
* ilo: unref old fenceRob Clark2015-07-101-0/+2
| | | | | | | | | Some, but not all, state trackers will explicitly unref (and set to NULL) the previous *fence before calling pipe->flush(). So driver should use fence_ref() which will unref the old fence if not NULL. Signed-off-by: Rob Clark <[email protected]> Acked-by: Chia-I Wu <[email protected]>
* freedreno: unref old fenceRob Clark2015-07-101-1/+3
| | | | | | | | Some, but not all, state trackers will explicitly unref (and set to NULL) the previous *fence before calling pipe->flush(). So driver should use fence_ref() which will unref the old fence if not NULL. Signed-off-by: Rob Clark <[email protected]>
* nv50: avoid segfault with enabled but unbound vertex attribSamuel Pitoiset2015-07-081-0/+5
| | | | | | | | | | | Before validating vertex arrays we need to check if a VBO is present. Checking if vb->buffer is not NULL fixes the issue. Fixes the following piglit test: gl-3.1-vao-broken-attrib Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: fix wrong use of BLIT_SRC_Y_INT for 2D texture copySamuel Pitoiset2015-07-081-1/+1
| | | | | | | | | | According to nv50, this should be src->ms_y instead of src->ms_x. This code is here since 2012, so it's probably a typo error which has never been detected since a long time. I didn't do a full piglit run to check if it fixes some other weird issues. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* android: freedreno: add missing components to the buildVarad Gautam2015-07-081-1/+4
| | | | | | | Freedreno requires {a4xx,ir3}_SOURCES and NIR to build. Signed-off-by: Varad Gautam <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* nvc0: turn sample counts off during blitIlia Mirkin2015-07-071-0/+7
| | | | | | | | | Fixes the following piglits: occlusion_query_meta_fragments occlusion_query_meta_no_fragments Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* radeonsi: Use param export count from si_llvm_export_vs in si_shader_vsMichel Dänzer2015-07-073-22/+6
| | | | | | | | | | | | This eliminates the error prone logic in si_shader_vs recalculating this value. It also fixes TGSI_SEMANTIC_CLIPDIST outputs incorrectly not being counted for VS exports. They need to be counted because they are passed to the pixel shader as parameters as well. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91193 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: don't flush an empty IB if the only thing we need is a fenceMarek Olšák2015-07-053-3/+15
| | | | Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: mark the gpu load thread stop trigger as volatileMarek Olšák2015-07-051-1/+1
|
* gallium: remove redundant pipe_context::fence_signalledMarek Olšák2015-07-0512-125/+0
| | | | | | fence_finish(timeout=0) does the same thing Reviewed-by: Brian Paul <[email protected]>
* gallium: handle fence_finish timeout in various driversMarek Olšák2015-07-055-0/+15
| | | | | | I copied what fence_signalled does. Reviewed-by: Brian Paul <[email protected]>
* radeonsi: fix a hang with DrawTransformFeedback on 4 SE chipsMarek Olšák2015-07-051-0/+4
| | | | | | Cc: 10.6 10.5 <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* nv50/ir: UCMP arguments are float, so make sure modifiers are appliedIlia Mirkin2015-07-031-1/+2
| | | | | | | | | The first argument to UCMP needs to be compared against 0, but the latter arguments are treated as float and need to be able to properly apply neg/abs arguments. Adjust the inferSrcType function accordingly. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-21 14:52:38 +0000