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* vc4: Try to schedule QIR instructions between writing to and reading math.Eric Anholt2016-11-301-0/+22
* vc4: Improve interleaving of texture coordinates vs results.Eric Anholt2016-11-301-3/+3
* vc4: Fix stray "." on no-op MUL packs.Eric Anholt2016-11-301-6/+6
* vc4: Allow merging instructions with SF set where the other writes NOP.Eric Anholt2016-11-301-0/+1
* vc4: In a loop break/continue, jump if everyone has taken the path.Eric Anholt2016-11-301-10/+17
* swr: add streamout buffer offset into pBuffer pointerIlia Mirkin2016-11-301-2/+3
* swr: fix assertion for max number of so targetsIlia Mirkin2016-11-301-1/+1
* swr: properly report max number of SO componentsIlia Mirkin2016-11-301-1/+1
* swr: turn off queries around blitsIlia Mirkin2016-11-301-1/+9
* swr: don't advertise stream pause/resumeIlia Mirkin2016-11-301-1/+1
* swr: fix range computation for instanced client-side arraysIlia Mirkin2016-11-302-24/+52
* swr: [rasterizer memory] assert when trying to convert an unknown formatIlia Mirkin2016-11-301-0/+1
* swr: remove warning about multi-layer surfacesIlia Mirkin2016-11-301-4/+0
* swr: [rasterizer core] don't attempt to load another RTAI when storingIlia Mirkin2016-11-301-1/+1
* radeonsi: apply the double EVENT_WRITE_EOP workaround to VI as wellMarek Olšák2016-12-011-2/+4
* radeonsi: add a tess+GS hang workaround for VI dGPUsMarek Olšák2016-12-011-2/+10
* radeonsi: don't apply the Z export bug workaround to HainanMarek Olšák2016-12-011-2/+3
* radeonsi: apply a tessellation bug workaround for SIMarek Olšák2016-12-011-0/+7
* radeonsi: apply a TC L1 write corruption workaround for SIMarek Olšák2016-12-011-11/+23
* radeonsi: apply a multi-wave workgroup SPI bug workaround to affected CIK chipsMarek Olšák2016-12-014-4/+29
* radeonsi: consolidate max-work-group-size computationMarek Olšák2016-12-011-24/+19
* freedreno/a5xx: fix negative branchesRob Clark2016-11-302-1/+6
* freedreno: fix android build with a5xxRob Clark2016-11-301-0/+1
* freedreno/a5xx: fix discardRob Clark2016-11-301-3/+4
* freedreno/a5xx: initial supportRob Clark2016-11-3033-17/+4470
* freedreno: update generated headersRob Clark2016-11-3010-100/+4125
* freedreno: make gmem tile size alignment configurableRob Clark2016-11-303-8/+17
* freedreno/ir3: don't offset inloc by 8Rob Clark2016-11-304-27/+15
* freedreno/a3xx: use new shader linkage helperRob Clark2016-11-301-27/+16
* freedreno/a4xx: use new shader linkage helperRob Clark2016-11-301-27/+16
* freedreno/ir3: add new helper for shader linkageRob Clark2016-11-301-0/+47
* gallium: add PIPE_CAP_TGSI_CAN_READ_OUTPUTSNicolai Hähnle2016-11-3015-0/+15
* swr: [rasterizer jit] use signed integer representation for logic opIlia Mirkin2016-11-291-5/+12
* swr: add missing rgbx8_srgb variantIlia Mirkin2016-11-291-0/+1
* swr: reorder renderable formats, add grouping commentsIlia Mirkin2016-11-291-65/+87
* swr: use util_copy_framebuffer_state helperIlia Mirkin2016-11-291-12/+1
* swr: enable cubemap arraysIlia Mirkin2016-11-291-1/+1
* swr: rearrange caps into limits/supported/unsupported groupsIlia Mirkin2016-11-291-129/+84
* swr: only store up to the LOD sizeIlia Mirkin2016-11-291-1/+3
* swr: [rasterizer common] add SwrTrace() and macrosTim Rowley2016-11-292-15/+95
* radeonsi: don't fetch 8 dwords for samplerBuffer and imageBufferMarek Olšák2016-11-291-51/+43
* radeonsi: disable XNACK to free 2 SGPRs on APUsMarek Olšák2016-11-291-1/+1
* radeonsi: count and report temp arrays in scratch separatelyMarek Olšák2016-11-292-4/+40
* radeonsi: don't try to eliminate trivial VS outputs for PS and CSMarek Olšák2016-11-291-1/+4
* radeonsi: disable RB+ blend optimizations for dual source blendingMarek Olšák2016-11-291-0/+11
* radeonsi: set CB_BLEND1_CONTROL.ENABLE for dual source blendingMarek Olšák2016-11-291-0/+4
* radeonsi: always set all blend registersMarek Olšák2016-11-291-5/+5
* radeonsi: set the smallest possible CB_TARGET_MASKMarek Olšák2016-11-291-5/+5
* radeonsi: don't print bodies of header-only packetsMarek Olšák2016-11-291-0/+4
* radeonsi: print unknown registers with correct formattingMarek Olšák2016-11-291-1/+2
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