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* vc4: Make the pack-to-unorm instructions be non-SSA.Eric Anholt2015-08-204-42/+36
* vc4: Allow QIR registers to be non-SSA.Eric Anholt2015-08-204-4/+10
* vc4: We can now move TEX_RESULT accesses across other r4 ops.Eric Anholt2015-08-201-16/+0
* nv50/ir: pre-compute BFE arg when both bits and offset are immIlia Mirkin2015-08-201-3/+9
* r600g: Fix handling of TGSI_OPCODE_ARR with SBGlenn Kennard2015-08-211-1/+1
* r600: Turn 'r600_shader_key' struct into unionEdward O'Callaghan2015-08-214-38/+42
* r600: Rewrite r600_shader_selector_key() to use a switch stmtEdward O'Callaghan2015-08-211-7/+17
* nv50/ir: Handle OP_CVT when folding constant expressionsTobias Klausmann2015-08-201-0/+78
* nvc0/ir: undo more shifts still by allowing a pre-SHL to occurIlia Mirkin2015-08-201-15/+33
* nvc0/ir: don't require AND when the high byte is being addressedIlia Mirkin2015-08-201-0/+12
* nvc0/ir: detect i2f/i2i which operate on specific bytes/wordsIlia Mirkin2015-08-204-4/+82
* nvc0/ir: detect AND/SHR pairs and convert into EXTBFIlia Mirkin2015-08-201-20/+46
* nv50/ir: support different unordered_set implementationsChih-Wei Huang2015-08-205-12/+57
* radeonsi: fix a typo as_es -> as_ls in a stringMarek Olšák2015-08-191-1/+1
* radeonsi: fix indirect indexing of MSAA texturesMarek Olšák2015-08-191-4/+13
* util/ra: Make allocating conflict lists optionalJason Ekstrand2015-08-183-3/+4
* freedreno: use fd_pipe_wait_timeout()Rob Clark2015-08-182-21/+1
* freedreno: fence fixRob Clark2015-08-183-4/+8
* radeon/uvd: remove unused variablesGrazvydas Ignotas2015-08-181-4/+1
* nouveau: recognize tess stages in nouveau_compilerMarcos Paulo de Souza2015-08-171-0/+4
* freedreno/a3xx: add s3tc texture format supportIlia Mirkin2015-08-171-0/+9
* freedreno/a3xx: fix up logic for handling block formatsIlia Mirkin2015-08-173-5/+7
* freedreno/a3xx: double the polygon offset valueIlia Mirkin2015-08-171-1/+1
* nvc0: implement the color buffer 0 is integer rule for alpha-to-one/covIlia Mirkin2015-08-173-11/+22
* gk110/ir: fix sched calculator to consider all registers in the ISAIlia Mirkin2015-08-171-7/+10
* nvc0: program smooth line width when multisampling is enabledIlia Mirkin2015-08-171-1/+1
* nvc0: bind a fake tess control program when there isn't one availableIlia Mirkin2015-08-174-8/+44
* gm107/ir: avoid letting the lowering pass get out of syncIlia Mirkin2015-08-172-88/+5
* nv50,nvc0: take level into account when doing eng2d multi-layer blitsIlia Mirkin2015-08-172-8/+20
* freedreno/a3xx: add per-texture seamless cubemap controlIlia Mirkin2015-08-162-1/+2
* freedreno/a4xx: add cube map array supportIlia Mirkin2015-08-154-4/+14
* freedreno/a4xx: fix srgb render targetsRob Clark2015-08-153-8/+22
* freedreno: update generated headersRob Clark2015-08-155-14/+30
* freedreno: expose OES exts for float linear filteringIlia Mirkin2015-08-141-2/+4
* nvc0: disable tessellation on maxwellIlia Mirkin2015-08-141-2/+5
* vc4: Move all of our fixed function fragment color handling to NIR.Eric Anholt2015-08-146-388/+538
* vc4: Add a helper for making driver-specific NIR load_uniform for GL stateEric Anholt2015-08-142-2/+30
* nir: Add a nir_opt_undef() to handle csels with undef.Eric Anholt2015-08-141-0/+1
* gm107/ir: indirect handle goes first on maxwell alsoIlia Mirkin2015-08-141-8/+4
* nv30: add depth bounds test support for hw that has itIlia Mirkin2015-08-143-2/+14
* nv50: add depth bounds test supportIlia Mirkin2015-08-143-2/+12
* nvc0: add depth bounds test supportIlia Mirkin2015-08-143-2/+9
* radeonsi: revert a wrong DB bug workaround for VIMarek Olšák2015-08-141-4/+0
* radeon/uvd: implement HEVC supportBoyuan Zhang2015-08-143-17/+298
* radeon/vce: disable VCE dual instance for harvest partLeo Liu2015-08-142-1/+4
* radeon/vce: implement VCE dual instance supportLeo Liu2015-08-143-5/+30
* radeon/video: config encode stacked frame number based on HWLeo Liu2015-08-141-0/+2
* radeon/vce: make reloc offset signedChristian König2015-08-144-6/+6
* radeon/vce: add config task and put task info into encoder v2Leo Liu2015-08-144-33/+47
* radeon/vce: fix VCE fail after rebaseLeo Liu2015-08-141-8/+6
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