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* radeonsi/gfx9: fix texture buffer objects and image buffers with IDXEN==0Marek Olšák2017-04-261-1/+34
| | | | | Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ddebug: implement get_query_result_resourceMarek Olšák2017-04-251-0/+16
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* trace: don't trace resource_destroyMarek Olšák2017-04-251-7/+4
| | | | | | | due to the lack of pipe_resource wrapping, we can get this call from inside of driver calls, which would try to lock an already-locked mutex. Reviewed-by: Nicolai Hähnle <[email protected]>
* freedreno/a5xx: hack for r8g8b8a8_snormRob Clark2017-04-231-1/+1
| | | | | | | | | Blob won't render to this format, and sampling from it it uses the same fmt value for r8g8b8_snorm and r8g8b8a8_snorm. But this is what is what blocks us from jumping from gl30/gles20 to gl31/gles30. So a hack it is! Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: rgtc formatsRob Clark2017-04-232-8/+12
| | | | Signed-off-by: Rob Clark <[email protected]>
* etnaviv: Supertiled texture support on gc3000Wladimir J. van der Laan2017-04-222-8/+11
| | | | | | | | | | | | | | | | | Support supertiled textures on hardware that has the appropriate feature flag SUPERTILED_TEXTURE. Most of the scaffolding was already in place in etna_layout_multiple: case ETNA_LAYOUT_SUPER_TILED: *paddingX = 64; *paddingY = 64; *halign = TEXTURE_HALIGN_SUPER_TILED; So this is just a matter of allowing it. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: etnaviv_fence: Simplify the return code logicFabio Estevam2017-04-221-4/+2
| | | | | | | The return code can be simplified by using the logical not operator. Signed-off-by: Fabio Estevam <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* freedreno/a5xx: occlusion queryRob Clark2017-04-224-3/+140
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: drop ring arg from _set_stage()Rob Clark2017-04-227-17/+13
| | | | | | | | It is always the draw ring. Except for a5xx queries like time-elapsed, where we will eventually want to emit cmds into both binning and draw rings. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-04-226-12/+25
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: add support for hw accumulating queriesRob Clark2017-04-228-33/+384
| | | | | | | | | | | | | Some queries on a4xx and all queries on a5xx can do result accumulation on CP so we don't need to track per-tile samples. We do still need to handle pausing/resuming while switching batches (in case the query is active over multiple draws which are executed out of order). So introduce new accumulated-query helpers for these sorts of queries, since it doesn't really fit in cleanly with the original query infra- structure. Signed-off-by: Rob Clark <[email protected]>
* freedreno: a bit of query refactorRob Clark2017-04-224-40/+40
| | | | | | | | Move a bit more of the logic shared by all query types (active tracking, etc) into common code. This avoids introducing a 3rd copy of that logic for a5xx. Signed-off-by: Rob Clark <[email protected]>
* freedreno: make hw-query a helperRob Clark2017-04-2213-16/+57
| | | | | | | | | For a5xx (and actually some queries on a4xx) we can accumulate results in the cmdstream, so we don't need this elaborate mechanism of tracking per-tile query results. So make it into vfuncs so generation specific backend can use it when it makes sense. Signed-off-by: Rob Clark <[email protected]>
* nvc0: Add support for setting viewport index/layer from VS/TESIlia Mirkin2017-04-204-7/+27
| | | | | | | | | | | | | This enables support on GM200+ for: - GL_AMD_vertex_shader_layer - GL_AMD_vertex_shader_layer_viewport_index - GL_ARB_shader_viewport_layer_array Signed-off-by: Ilia Mirkin <[email protected]> [lyude: add relnotes/TES cap] Signed-off-by: Lyude <[email protected]> [imirkin: move relnotes to right place, add features.txt] Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0/ir: Only store viewport in scratch register for GPLyude2017-04-201-0/+1
| | | | | | | | | EMIT only applies to geometry shaders. For everything else, we want to export the viewport normally. Signed-off-by: Lyude <[email protected]> Reviewed-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: fold u_trim_pipe_prim call from st/mesa to driversMarek Olšák2017-04-208-0/+38
| | | | | | | Most drivers don't need it and shouldn't need it because it can't be used in some cases (indirect draws, primitive restart, count from streamout). Reviewed-by: Brian Paul <[email protected]>
* swr: simd16 vs workTim Rowley2017-04-191-5/+25
| | | | | | | Build VS with alternating output for the current simd16 fe double-pump of a simd8 shader. Reviewed-by: Bruce Cherniak <[email protected]>
* r600g: update dirty_level_mask after the 1-st draw after FB changeConstantine Kharlamov2017-04-194-18/+26
| | | | | | | | | | | Ported from radeonsi. Testing with Kane&Lynch2 shows ≈1k skipped updates per frame on average. No piglit changes with tests/gpu.py, gbm mode. Signed-off-by: Constantine Kharlamov <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* freedreno: refactor dirty state handlingRob Clark2017-04-1819-101/+119
| | | | | | | | In particular, move per-shader-stage info out to a seperate array of enum's indexed by shader stage. This will make it easier to add more shader stages as well as new per-stage state (like SSBOs). Signed-off-by: Rob Clark <[email protected]>
* freedreno: move clear path dirty state hack to a2xx backendRob Clark2017-04-182-9/+9
| | | | | | | | | a3xx/a4xx use the generic u_blitter path, which will make state dirty bits be set appropriately thanks to the automagic of generic code setting generic state in the driver. And a5xx has a blit/dma engine (actually, two) so it doesn't need these extra dirty bits set. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split out per-stage emit_consts fxnsRob Clark2017-04-185-21/+41
| | | | | | | | | This makes it easier to deal with adding additional stages which have their own driver-params. The duplicated code this introduces can be refactored out after a later patch moves to per-shader-stage dirty flags. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add helper to mark all state cleanRob Clark2017-04-189-52/+34
| | | | | | | | Note that this involves juggling around a bit when we emit and clear texture state. So split out from the patch that adds the helper to set all state dirty. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add helper to mark all state dirtyRob Clark2017-04-184-6/+13
| | | | | | This will simplify things when we break out per-shader-stage dirty bits. Signed-off-by: Rob Clark <[email protected]>
* freedreno: move a2xx specific hack out of coreRob Clark2017-04-182-10/+20
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: make texture state an arrayRob Clark2017-04-1810-39/+45
| | | | | | | | Make this an array indexed by shader stage, as is done elsewhere for other per-shader-stage state. This will simplify things as more shader stages are eventually added. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: refactor out helpers for comparing shader keysRob Clark2017-04-184-79/+63
| | | | | | | | | | | | Each of the ir3 users has *basically* the same logic for comparing the previous and current shader key, to see which, if any, shader state needs to be marked dirty due to shader variant change. The difference between gen's was just that some lowering flags never get set on certain generations. But it doesn't really hurt to include the extra checks (because both keys would have false). Signed-off-by: Rob Clark <[email protected]>
* vc4: Enable V3D 2.6.Eric Anholt2017-04-181-1/+1
| | | | | This version of the chip is present on the Cygnus-based 911360 enterprise phone platform. It appears to be completely backwards compatible.
* freedreno: fix crash if ctx torn down with no renderingRob Clark2017-04-171-1/+1
| | | | | | | | In this case, ctx->flush_queue would not have been initialized. Fixes: 0b613c20 ("freedreno: enable draw/batch reordering by default") Cc: "17.1" <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add 'high' register classRob Clark2017-04-173-67/+131
| | | | | | | | For compute shaders, we need to be able to allocate some "high" registers (r48.x to r55.w). (Possibly these are global to all threads in a warp?) Add a new register class to handle this. Signed-off-by: Rob Clark <[email protected]>
* freedreno: extract helper for stage->sb for a4xx+Rob Clark2017-04-175-28/+29
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/{a4xx,a5xx}: switch to CP_LOAD_STATE4Rob Clark2017-04-175-127/+124
| | | | | | | The layout of CP_LOAD_STATE packet is slightly different on a4xx+. Switch to the a4xx+ specific CP_LOAD_STATE4 to get the correct encoding. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-04-178-213/+794
| | | | Signed-off-by: Rob Clark <[email protected]>
* gallium/radeon: always flush asynchronously and wait after begin_new_csMarek Olšák2017-04-172-4/+11
| | | | | | | | | | This hides the overhead of everything in the driver after the CS flush and before returning from pipe_context::flush. Only microbenchmarks will benefit. +2% FPS for glxgears. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove local variable 'mod' from si_compile_tgsi_shaderMarek Olšák2017-04-171-5/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add si_shader_selector::vs_needs_prologMarek Olšák2017-04-173-7/+10
| | | | | | cleanup Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't set VGT_GS_MODE as part of the GS stateMarek Olšák2017-04-171-2/+0
| | | | | | The VS state sets it. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't allow user indices with indirect drawsMarek Olšák2017-04-171-4/+4
| | | | | | | Not possible with GL and it will make future gallium rework easier. (also it's something I wouldn't like to support) Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: merge two if (indirect) statementsMarek Olšák2017-04-171-27/+25
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't mark non-dirty textures with CMASK as compressedMarek Olšák2017-04-171-2/+3
| | | | | | | because the compression is skipped with non-dirty textures. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* etnaviv: native fence fd supportPhilipp Zabel2017-04-156-6/+82
| | | | | | | | | | This adds native fence fd support to etnaviv, similarly to commit 0b98e84e9ba0 ("freedreno: native fence fd"), enabled for kernel driver version 1.1 or later. Signed-off-by: Philipp Zabel <[email protected]> Reviewed-By: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: SINGLE_BUFFER support on GC3000Wladimir J. van der Laan2017-04-158-28/+63
| | | | | | | | | | | | | | | | | | | | This patch adds support for the SINGLE_BUFFER feature on GC3000 GPUs, which allows rendering to a single buffer using multiple pixel pipes. This feature is always used when it is available, which means that multi-tiled formats are no longer being used in that case, and all buffers will be normal (super)tiled. This mimics the behavior of the blob on GC3000. - Because the same format can be used to render to and texture from, this avoids an extra resolve pass when rendering to texture. - i.MX6qp includes a PRE which can scan-out directly from tiled formats, avoiding untiling overhead. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: Update includes from rnndbWladimir J. van der Laan2017-04-155-20/+91
| | | | | | | | | Update to etna_viv commit 8486a97. austriancoder: changed patch to include isa redefinition fix. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: Add chipMinorFeatures4 and 5Wladimir J. van der Laan2017-04-152-1/+15
| | | | | | | | Request chipMinorFeatures bitfields 4 and 5 from the drm driver. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: resolve tile status when flushing resourcePhilipp Zabel2017-04-152-0/+11
| | | | | | | | | | | | | | | | When passing render buffers from EGL clients to a wayland compositor, the resource tile status must be resolved because otherwise the tile status is lost in the transfer and cleared parts of the buffer will contain old contents. The same applies when sampling directly from a renderable resource. lst: Add seqno tracking, to skip flush when not needed. Fixes: aadcb5e94b35 ("etnaviv: enable TS, but disable autodisable") Signed-off-by: Philipp Zabel <[email protected]> Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: stop repeatedly resolving an unchanged resource into its scanout ↵Philipp Zabel2017-04-151-1/+4
| | | | | | | | | | | prime buffer Before resolving a resource into its scanout prime buffer, check that the prime resource is actually older. If it is not, the resolve is an expensive no-op, and we better skip it. Signed-off-by: Philipp Zabel <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* swr: Add polygon stipple supportGeorge Kyriazis2017-04-145-9/+84
| | | | | | | | | Add polygon stipple functionality to the fragment shader. Explicitly turn off polygon stipple for lines and points, since we do them using tris. Reviewed-by: Bruce Cherniak <[email protected]>
* radeonsi: add missing initialization for userptr buffersNicolai Hähnle2017-04-141-0/+4
| | | | | | | | | | | | | | | | Fix the accounting for memory usage of userptr buffers, which has been wrong forever (or at least for a long time). Also initialize flags. Without this initialization, the sparse buffer flag might end up being set, which leads to staging buffers being used unnecessarily (and incorrectly) in transfers to or from userptr buffers. This works around VM faults that occur with the radeon kernel module when running piglit ./bin/amd_pinned_memory decrement-offset map-buffer -auto Fixes: e077c5fe6579 ("gallium/radeon: transfers and invalidation for sparse buffers") Reported-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: cope with missing disassemblyNicolai Hähnle2017-04-141-1/+2
| | | | | | For robustness and testing purposes. Reviewed-by: Marek Olšák <[email protected]>
* gallium/ddebug: dump missing members of pipe_draw_infoNicolai Hähnle2017-04-141-0/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: enable ARB_shader_viewport_layer_arrayNicolai Hähnle2017-04-141-1/+1
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
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