| Commit message (Collapse) | Author | Age | Files | Lines |
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12.0 and older need the same fix but elsewhere.
Cc: 13.0 <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
Cc: 11.2 12.0 13.0 <[email protected]>
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The emitter tried to emit sub instead of subr when src0 has
actually a NEG modifier.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
Cc: "11.0 12.0 13.0" <[email protected]>
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This affects GF100:GK110 chipsets, but not GM107+ where the
logic is a bit different. The emitters tried to emit sub
instead of subr when src0 has a NEG modifier.
This fixes the following piglit tests glsl-fs-loop-nested
and glsl-vs-loop-nested.
Signed-off-by: Samuel Pitoiset <[email protected]>
Acked-by: Ilia Mirkin <[email protected]>
Cc: "13.0" <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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it has no effect whatsoever
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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GCN can use a completely different tile mode for FMASK.
FMASK allocation now skips one unrelated amdgpu_surface_init codepath as
hinted by the assertion.
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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fmask implies that cmask is present too.
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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these names were misleading.
Reviewed-by: Nicolai Hähnle <[email protected]>
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These just say whether libdrm can assume that the latest radeon_surface
definition is used by Mesa.
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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This removes input-only parameters from the radeon_surf structure.
Some of the translation logic from pipe_resource to radeon_surf is moved to
winsys/radeon.
Reviewed-by: Nicolai Hähnle <[email protected]>
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npix_y will be removed. level[0].npix_y will be removed too. nblk_y should
be the same as npix_y if the block height == 1. However, nblk_y is aligned
to the tile size, so it can be greater than npix_y.
If that's a problem, we'll have to save the input height of surface_init
and use that.
Reviewed-by: Christian König <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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SDMA might be fixed by:
"winsys/amdgpu: fix radeon_surf::macro_tile_index for imported textures"
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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This should fix random GPU hangs on Hawaii and Fiji.
Cc: 11.2 12.0 13.0 <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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Oh my god, I wonder what catastrophic issues this was causing on SI.
Cc: 13.0 <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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When restoring something from shader cache we won't have and don't
want to create a nir_shader this change detaches the two.
There are other advantages such as being able to reuse the
shader info populated by GLSL IR.
Reviewed-by: Jason Ekstrand <[email protected]>
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total instructions in shared programs : 3499888 -> 3499445 (-0.01%)
total gprs used in shared programs : 453866 -> 453803 (-0.01%)
total local used in shared programs : 21621 -> 21621 (0.00%)
total bytes used in shared programs : 32078952 -> 32074936 (-0.01%)
local gpr inst bytes
helped 0 39 119 119
hurt 0 0 0 0
Signed-off-by: Karol Herbst <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
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Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
Cc: "12.0 13.0" <[email protected]>
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Shared memory is local to CTA, thus we should only wait for
prior memory writes which are visible to other threads in
the same CTA, and not at global level. This should speedup
compute shaders which use shared memory.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
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Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
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nvdisasm does not print a .S even though the bit is set.
Signed-off-by: Ilia Mirkin <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
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radeonsi also does the same thing. I suspect that this is likely to be a
no-op in reality, but it brings nouveau code closer to what the blob
produces. Plus it makes sense to not try to do auto-derivatives on this.
Signed-off-by: Ilia Mirkin <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
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This allows the driver to signal that it can't handle random
interleaving of attributes across buffers. This is required for
ARB_transform_feedback3, and it's initialized to whatever the previous
value of PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME was except for nv50 where
it is disabled. Note that the proprietary drivers never expose
ARB_transform_feedback3 on any GT21x's (where nouveau previously did),
and after some effort I was unable to get it to work.
Signed-off-by: Ilia Mirkin <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
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Getting stores to NIR regs to not generate new MOVs is tricky, since the
result we're trying to store into the NIR reg may have been from a
conditional update of a temp, or a series of packed writes. The easiest
solution seems to be to require that nir_store_dest()'s arg comes from an
SSA temp.
This causes us to put in a few more temporary MOVs in the NIR SSA dest
case, but copy propagation successfully cleans those up.
The shader-db change is modest:
total instructions in shared programs: 93774 -> 93598 (-0.19%)
instructions in affected programs: 14760 -> 14584 (-1.19%)
total estimated cycles in shared programs: 212135 -> 211946 (-0.09%)
estimated cycles in affected programs: 27005 -> 26816 (-0.70%)
but I was seeing patterns in some register-allocation failures in DEQP
tests that looked like the extra MOVs would increase maximum register
pressure in loops. Some debug code indicates that that's not the case,
though I'm still a bit confused by that result.
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One tiny hack is left in vc4_bufmgr.c for what kind of mapping we got so
that we can free it.
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Now we aren't limited to 256MB total allocated across a driver instance,
just 256MB at one time. We're still copying in and out, which should get
fixed.
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I would like to put a couple more things in here, so it's time to package
it up.
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Rather than having simulator mode changes scattered around vc4_bufmgr.c
and vc4_screen.c, make vc4_bufmgr.c just call a vc4_simulator_ioctl, which
then dispatches to a corresponding implementation.
This will give the simulator support a centralized place to do tricks like
storing most BOs directly in simulator memory rather than copying in and
out.
This leaves special casing of mmaping BOs and execution, because of the
winsys mapping.
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The loop is scanning until the original max_ip (size of the BO), but we
want to not examine any code after the PROG_END's delay slots. There was
a block trying to do that, except that we had some early continue
statements if the signal wasn't a PROG_END or a BRANCH.
The failure mode would be that a valid shader is rejected because some
undefined memory after the PROG_END slots is parsed as a branch and the
rest of its setup is illegal. I haven't seen this in the wild, but
valgrind was complaining and the new userland simulator code started
triggering it.
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A constant value of float type is not necessarily a ConstantFP: it could also
be a constant expression that for some reason hasn't been folded.
This fixes a regression in GL45-CTS.arrays_of_arrays_gl.InteractionFunctionCalls2
that was introduced by commit 3ec9975555d1cc5365413ad9062f412904f944a3.
Reviewed-by: Marek Olšák <[email protected]>
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This reverts commits 1af0641db345209c076e9b1ba4dca7524541671a and
a6ad49cbbd599aec054d0a3163fff5ad724f2b18.
st/mesa adjusts the rasterizer state for us now.
Signed-off-by: Ilia Mirkin <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
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Long story short, 3D and CP are aliased on Fermi and initializing
compute after pushing the MS sample coordinate offsets seems to
corrupt 3D state for weird reasons.
I still don't have the faintest clue what is going on, but
this seems to only affect Fermi generation. A possible fix
could be to use two different channels, one for 3D and one
for CP.
This fixes a bunch of regressions pinpointed by piglit.
Fixes: "nvc0: fix up image support for allowing multiple samples"
Cc: "13.0" <[email protected]>
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
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This makes shader-db reports results for compute shaders.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
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Reviewed-by: Nicolai Hähnle <[email protected]>
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