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* nvc0: enable ARB_enhanced_layoutsSamuel Pitoiset2016-10-131-1/+1
* radeonsi: adjust and clean up Z_ORDER and EXEC_ON_x settingsMarek Olšák2016-10-132-22/+32
* radeonsi: disable ReZMarek Olšák2016-10-131-7/+4
* radeonsi: implement TC-compatible HTILEMarek Olšák2016-10-138-20/+132
* radeonsi: fix regression in image atomicsNicolai Hähnle2016-10-131-1/+1
* radeonsi: fix the coordinate overloading of llvm.amdgcn.image.atomic.cmpswap.*Nicolai Hähnle2016-10-131-2/+7
* swr: automake: add ar_eventhandlerfile_h.template to the tarballEmil Velikov2016-10-121-1/+2
* nvc0/ir: fix textureGather with a single offsetIlia Mirkin2016-10-121-2/+2
* nv50/ir: copy over value's register id when resolving merge of a phiIlia Mirkin2016-10-121-1/+3
* st/mesa: enable ARB_enhanced_layouts and turn the cap onNicolai Hähnle2016-10-123-3/+3
* gallium: add PIPE_CAP_TGSI_ARRAY_COMPONENTSNicolai Hähnle2016-10-1215-0/+15
* radeonsi: Use the new image load/store intrinsic signaturesTom Stellard2016-10-121-14/+45
* radeonsi: Add function for converting LLVM type to intrinsic stringTom Stellard2016-10-121-10/+32
* radeonsi: Refactor image store/load intrinsic name creationTom Stellard2016-10-121-11/+18
* radeonsi: fix R600_DEBUG=precompile for shader-dbMarek Olšák2016-10-121-0/+6
* radeonsi: use TC write-back instead of full cache invalidationMarek Olšák2016-10-123-13/+7
* radeonsi: implement TC L2 write-back (flush) without cache invalidationMarek Olšák2016-10-122-28/+74
* radeonsi: don't invalidate VMEM L1 for memory barriers for index buffersMarek Olšák2016-10-121-3/+4
* nv50/ir: optimize ADD(SHL(a, b), c) to SHLADD(a, b, c)Samuel Pitoiset2016-10-121-0/+87
* trace: add invalidate_resource callbackIlia Mirkin2016-10-111-0/+21
* radeonsi: emit TA_CS_BC_BASE_ADDR on SI only if the kernel allows itMarek Olšák2016-10-111-1/+6
* swr: [rasterizer archrast] update proto fileTim Rowley2016-10-111-2/+56
* swr: [rasterizer archrast] add support for stats filesTim Rowley2016-10-114-20/+57
* swr: [rasterizer jitter] remove architecture overrideTim Rowley2016-10-111-41/+1
* swr: [rasterizer jitter] adjust jitmanager assertTim Rowley2016-10-111-1/+4
* swr: [rasterizer] eliminate unused label warnings on gccTim Rowley2016-10-112-0/+8
* swr: [rasterizer core] implement depth bounds testTim Rowley2016-10-116-9/+101
* swr: [rasterizer core] update/add formatsTim Rowley2016-10-117-1705/+2592
* swr: [rasterizer core] SwrStoreTiles api changeTim Rowley2016-10-117-19/+27
* swr: [rasterizer scripts] add ENABLE_ASSERT_DIALOGS knob for windowsTim Rowley2016-10-111-0/+8
* swr: [rasterizer archrast] add mako templateTim Rowley2016-10-114-2/+117
* swr: [rasterizer core] disable cull for rect_listTim Rowley2016-10-111-0/+8
* swr: [rasterizer core] add support for "RAW" surface formatTim Rowley2016-10-112-0/+29
* swr: [rasterizer core] align Macrotile FIFO memory to SIMD sizeTim Rowley2016-10-114-9/+23
* swr: [rasterizer common] remove threadviz codeTim Rowley2016-10-113-94/+0
* swr: [rasterizer memory] split load/store for compile speedTim Rowley2016-10-1117-1836/+2290
* i915g: fix incorrect gl_FragCoord valueNicholas Bishop2016-10-101-1/+6
* softpipe: Cap to 2 GB on 32 bitsAxel Davy2016-10-101-0/+6
* llvmpipe: Cap to 2 GB on 32 bitsAxel Davy2016-10-101-0/+6
* nvc0: fix valid range for shader buffersSamuel Pitoiset2016-10-103-0/+3
* nvc0/ir: fix overwriting of value backing non-constant gather offsetIlia Mirkin2016-10-101-2/+2
* nv50/ir: only stick one preret per functionIlia Mirkin2016-10-101-4/+7
* radeonsi: make more use of si_have_tgsi_computeNicolai Hähnle2016-10-101-3/+1
* gallium/radeon: assign a name to LLVM output variables in debug buildsNicolai Hähnle2016-10-101-1/+6
* gallium/radeon: avoid redundant work with overlapping in/out arraysNicolai Hähnle2016-10-101-1/+4
* radeonsi: support ARB_compute_variable_group_sizeNicolai Hähnle2016-10-105-17/+53
* gallium: add missing zero-init for resource templatesRob Clark2016-10-071-0/+1
* freedreno: don't try to shadow layered texturesRob Clark2016-10-071-0/+3
* freedreno/a3xx+a4xx: fix clip-plane lowering stateRob Clark2016-10-072-0/+6
* vc4: Don't worry about partial Z/S clear if the other is already cleared.Eric Anholt2016-10-061-3/+7
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