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* radeon/llvm: Remove AMDIL VCREATE* instructionsTom Stellard2012-06-068-97/+12
* radeon/llvm: Remove AMDIL LOADCONST* instructionsTom Stellard2012-06-0613-322/+33
* nouveau: fix scratch buffer leakMarcin Slusarz2012-06-054-3/+15
* nv50: fix nv50_stream_output_state leakMarcin Slusarz2012-06-051-0/+3
* nv50: fix symbol table memory leakMarcin Slusarz2012-06-051-0/+3
* radeon/llvm: Fix VTX_READ patternsTom Stellard2012-06-013-4/+33
* radeon/llvm: Emit 2 bytes for vertex fetch offsetsTom Stellard2012-06-012-1/+3
* radeon/llvm: Only use indirect (vertex fetch) parameters for kernelsTom Stellard2012-06-011-2/+6
* radeon/llvm: Eliminate CFGStructurizer dependency on AMDIL instructionsTom Stellard2012-06-0111-41/+124
* radeon/llvm: Change prefix on tablegen files to AMDGPUTom Stellard2012-06-0117-50/+50
* radeon/llvm: Remove deadcode from the R600LowerInstructions passTom Stellard2012-06-011-46/+2
* radeon/llvm: Remove AMDIL GLOBALSTORE* instructionsTom Stellard2012-06-014-77/+36
* radeon/llvm: Remove AMDIL GLOBALLOAD* instructionsTom Stellard2012-06-016-128/+24
* r600g: compute support for evergreenAdam Rak2012-06-0120-12/+2674
* svga: fix saturated TEX instructionsBrian Paul2012-05-311-6/+13
* draw: simplify index buffer specificationBrian Paul2012-05-319-28/+28
* nv50: hook up forgotten short constant buffer upload methodMarcin Slusarz2012-05-291-0/+1
* radeon/llvm: Update and fix some commentsTom Stellard2012-05-292-12/+6
* radeonsi: Remove use.sgpr* intrinsics, use load instructions insteadTom Stellard2012-05-295-74/+57
* radeonsi: Handle TGSI CONST registersTom Stellard2012-05-2912-100/+254
* radeon/llvm: Remove AMDILIntrinsicInfo::GetDeclaration fuction bodyTom Stellard2012-05-291-20/+1
* radeon/llvm: Remove AMDILTargetMachineTom Stellard2012-05-2919-363/+90
* nouveau: unreference fences on resource destructionChristoph Bumiller2012-05-292-0/+6
* nvc0: optimize blend cso by checking which by-RT data actually differsChristoph Bumiller2012-05-291-65/+94
* nvc0: don't upload UCPs if the shader doesn't use themChristoph Bumiller2012-05-291-1/+1
* nvc0/ir: allow 64-bit constant loads on nve4Christoph Bumiller2012-05-292-1/+3
* nvc0/ir: fix texture barrier insertion to prevent WAW hazardsChristoph Bumiller2012-05-296-29/+88
* nvc0/ir: TEX doesn't support JOIN modifier eitherChristoph Bumiller2012-05-291-0/+1
* nv30: Fix generic passing to fragment program in NV34.Roy Spliet2012-05-253-5/+9
* nv30: handle user index buffersChristoph Bumiller2012-05-254-17/+27
* radeon/llvm: Use a custom inserter for MASK_WRITETom Stellard2012-05-254-34/+36
* radeon/llvm: Use tablegen pattern to lower bitconvertTom Stellard2012-05-254-294/+11
* radeon/llvm: Use a custom inserter to lower FNEGTom Stellard2012-05-255-22/+15
* radeon/llvm: Use a custom inserter to lower CLAMPTom Stellard2012-05-259-84/+41
* radeon/llvm: Use a custom inserter to lower FABSTom Stellard2012-05-2510-42/+41
* r600g: handle R16G16B16_FLOAT and R32G32B32_FLOAT in translate_colorswapKai Wasserbäch2012-05-251-0/+2
* svga: remove the special zero-stride vertex array codeBrian Paul2012-05-259-153/+12
* Revert "r600g: set round_mode to truncate and get rid of tgsi_f2i on evergreen"Vadim Girlin2012-05-252-6/+56
* radeon/llvm: add FLT_TO_UINT, UINT_TO_FLT instructionsVadim Girlin2012-05-251-0/+20
* radeon/llvm: prepare to revert the round mode state to defaultVadim Girlin2012-05-251-2/+9
* radeon/llvm: fix sampler index in llvm_emit_texVadim Girlin2012-05-251-2/+4
* radeon/llvm: fix opcode for RECIP_UINT_r600Vadim Girlin2012-05-251-1/+1
* radeon/llvm/loader: convert hardcoded gpu name to optionVadim Girlin2012-05-251-2/+3
* r600g: add RECIP_INT, PRED_SETE_INT to r600_bytecode_get_num_operandsVadim Girlin2012-05-251-0/+2
* i915g: Check for geometry shader earlier in i915_set_constant_buffer.Vinson Lee2012-05-241-4/+4
* radeon/llvm: Lower UDIV using the Selection DAGTom Stellard2012-05-248-212/+126
* radeon/llvm: Remove auto-generated AMDIL->ISA conversion codeTom Stellard2012-05-2414-280/+28
* radeon/llvm: Remove AMDIL instructions MULHI, SMULTom Stellard2012-05-243-10/+5
* radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR)Tom Stellard2012-05-248-693/+6
* radeon/llvm: Remove AMDIL FTOI and ITOF instructionsTom Stellard2012-05-247-316/+7
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