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* radeonsi/gfx9: fix VM fault with fetched instance divisorsNicolai Hähnle2017-11-202-5/+12
| | | | | | | | | We need to account for SGPR locations in merged shaders. This case is exercised by KHR-GL45.enhanced_layouts.vertex_attrib_locations Fixes: 79c2e7388c7f ("radeonsi/gfx9: use SPI_SHADER_USER_DATA_COMMON") Reviewed-by: Marek Olšák <[email protected]>
* broadcom/vc5: Fix up integer texture handling.Eric Anholt2017-11-191-27/+28
| | | | | | | | The original spec I had didn't expose integer textures and suggested that you use unfiltered floats. Now there are proper formats for them. Fixes 16- and 32-bit texwrap integer tests in piglit, and dEQP-GLES3.functional.fbo.completeness.renderable.renderbuffer.color0.rgb10_a2ui.
* broadcom/vc5: Fix simulator assertion failures about color RT clears.Eric Anholt2017-11-191-2/+19
| | | | | | | | When we tried to clear color while storing depth, it assertion failed about basically not having enough information to decide which color RT to clear. It turns out the STORE_GENERAL picks the buffer according to the color buffer being stored, or all of them if NONE. If you're doing depth, it doesn't know which to pick.
* freedreno/ir3: add texture gather supportRob Clark2017-11-182-2/+17
| | | | Signed-off-by: Rob Clark <[email protected]>
* etnaviv: enable full overwrite when no color buffer is presentLucas Stach2017-11-182-3/+3
| | | | | | | | The OVERWRITE bit disables destination fetches, which is exactly what we want when there is no valid color buffer bound. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]>
* broadcom/vc5: Set up the padded height at surface creation time.Eric Anholt2017-11-173-16/+15
| | | | | This centralizes the calculation in the surface, instead of in each load/store.
* broadcom/vc5: Fix clear color for swap_color_rb render targets.Eric Anholt2017-11-171-0/+9
| | | | Fixes dEQP-GLES3.functional.depth_stencil_clear.depth.*
* broadcom/vc5: Fix pasteo in front stencil ref value setup.Eric Anholt2017-11-171-1/+1
| | | | Fixes piglit masked-clear.
* broadcom/vc5: Fix colormasking when we need to swap r/b colors.Eric Anholt2017-11-171-9/+24
| | | | Fixes part of piglit masked-clear.
* broadcom/vc5: Enable the Z min/max clipping planes.Eric Anholt2017-11-171-2/+0
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* broadcom/vc5: Fix driver for new PIPE_SHADER_CAP_MAX_HW_ATOMIC_*.Eric Anholt2017-11-171-0/+2
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* r300: add PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER* switch casesBrian Paul2017-11-171-0/+2
| | | | | | To silence compiler warnings. Reviewed-by: Marek Olšák <[email protected]>
* radeon/video: enable encode support for ravenBoyuan Zhang2017-11-171-1/+2
| | | | | | | Enable h.264 encode for vcn hardware (raven) Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: enable vcn encodeBoyuan Zhang2017-11-171-1/+3
| | | | | | | Enable vcn encode by creating radeon_encoder for vcn. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add create encoderBoyuan Zhang2017-11-171-1/+81
| | | | | | | Add implementation for create_encoder interface for vcn encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode get feedbackBoyuan Zhang2017-11-171-1/+14
| | | | | | | Add implementation for get_feedback interface for vcn encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode destroyBoyuan Zhang2017-11-171-1/+15
| | | | | | | Add implementation for destroy interface for vcn encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode end frameBoyuan Zhang2017-11-171-1/+2
| | | | | | | Add implementation for end_frame interface for vcn encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode bitstreamBoyuan Zhang2017-11-171-1/+13
| | | | | | | Add implementation for encode_bitstream interface for vcn encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode begin frameBoyuan Zhang2017-11-171-1/+22
| | | | | | | Add implementation for begin_frame interface for vcn encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode header implementationsBoyuan Zhang2017-11-172-0/+241
| | | | | | | | Implement encoding of sps, pps, and silce headers using the newly added h.264 header coding descriptors functions based on h.264 specs. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add encode header algorithmsBoyuan Zhang2017-11-172-0/+127
| | | | | | | | | | | | Since bitstream headers, e.g. sps, pps, slice, are encoded in driver side, we need to add corresponding algorithms that required to generate those headers. According to h.264 specs, signed/unsigned interger Exp-Golomb-coded syntax element with left bit first (code_se and code_ue) and unsigned integer using n bits (code_fixed_bits) descriptors function are needed. Therefore, adding those algorithms and related variables and output algorithms here. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add ib implementationsBoyuan Zhang2017-11-171-24/+268
| | | | | | | Implement required ibs and command buffer submission interfaces for vcn encode Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add common encode partBoyuan Zhang2017-11-175-0/+489
| | | | | | | | | Add a skeleton pipe video interface and encode ib interface for video encode on vcn hardware. Add function defines and structures for vcn encode. Update Makefile.sources and meson.build with newly added files. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/winsys: add vcn enc ring typeBoyuan Zhang2017-11-171-0/+1
| | | | | | | New ring type is needed for vcn encode Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add vcn encode interfaceBoyuan Zhang2017-11-171-0/+325
| | | | | | | Add a new header file for vcn encode interface Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* freedreno/a5xx: stencil texturing supportRob Clark2017-11-173-10/+34
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx/gmem: fix z32/s8 restore/resolveRob Clark2017-11-171-5/+13
| | | | | | | BLIT_ZS mode is used for either combined z24/s8 or z32 in which case BLIT_S mode is used for separate stencil. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx/gmem: move ZS restore tiling hackRob Clark2017-11-171-20/+22
| | | | | | Code motion to simplify next patch. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-11-176-13/+13
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* svga: add missing PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER* casesBrian Paul2017-11-161-0/+2
| | | | | Reviewed-by: Charmaine Lee <[email protected]> Acked-by: Dave Airlie <[email protected]>
* r600: enable ARB_shader_image_load_store, ARB_shader_image_sizeDave Airlie2017-11-171-3/+9
| | | | | | | This also enables GL4.2 for gpus with hw fp64 (cayman, cypress) Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: handle image size support.Dave Airlie2017-11-173-9/+101
| | | | | | | | This adds support for the RESQ opcode with the workaround required due to hw bugs for buffers and cube arrays. Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/sb: disable SB for images.Dave Airlie2017-11-171-0/+1
| | | | | | | Until we can work further on sb, disable it for images for now. Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: add support for load/store/atomic ops on images.Dave Airlie2017-11-171-4/+315
| | | | | | | | This adds support to the shader assembler for load/store/atomic ops on images which are handled via the RAT operations. Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: add core pieces of image support.Dave Airlie2017-11-176-3/+428
| | | | | | | | | This adds the atoms and gallium api implementations, along with support for compress/decompress paths for shader images. Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: implement getting thread id.Dave Airlie2017-11-171-0/+74
| | | | | | | | We need the thread id to use the immediate buffer readback mechanism, so add support for calculating it. Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: add flag to denote if shader uses imagesDave Airlie2017-11-172-0/+2
| | | | | Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: implement basic memory barrier.Dave Airlie2017-11-172-5/+24
| | | | | | | | This isn't 100% perfect (fglrx also fails a bunch of those tests) but implement the start of a memory barrier for image support. Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: allocate immed buffer resource for images.Dave Airlie2017-11-173-0/+21
| | | | | | | | | In order to image readback we have to execute a MEM_RAT instruction that needs a buffer to transfer the result into until the shader can fetch it. Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: handle writes_memory properlyDave Airlie2017-11-172-3/+13
| | | | | | | This implements proper handling for shaders with side effects. Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* freedreno: also mark images used by draw/gridRob Clark2017-11-161-0/+18
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: mark SSBOs written at draw timeRob Clark2017-11-161-1/+1
| | | | | | Comment was right, implementation was wrong ;-) Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: ARB_framebuffer_no_attachments supportRob Clark2017-11-163-1/+11
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeonsi: copy some nir gs infoTimothy Arceri2017-11-161-0/+7
| | | | | | v2: copy input primitive Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: add gs_{prim,invocation}_id to the abiTimothy Arceri2017-11-162-10/+6
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: gather stream info in nir pathTimothy Arceri2017-11-161-0/+37
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* svga: s/unsigned/enum tgsi_texture_type/Brian Paul2017-11-151-5/+5
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* svga: issue debug warning for unsupported two-sided stencil stateBrian Paul2017-11-151-0/+15
| | | | | | | | | We only have a single stencil read mask and write mask. Issue a warning if different front/back values are used. The Piglit gl-2.0-two-sided-stencil test hits this. Reviewed-by: Neha Bhende <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* etnaviv: Add sampler TS supportWladimir J. van der Laan2017-11-153-6/+99
| | | | | | | | | | | | | Sampler TS is an hardware optimization that can be used when rendering to textures. After rendering to a resource with TS enabled, the texture unit can use this to bypass lookups to empty tiles. This also means a resolve-in-place can be avoided to flush the TS. This commit is also an optimization when not using sampler TS, as resolve-in-place will now be skipped if a resource has no (valid) TS. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
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