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* radeonsi/gfx9: don't set gs_table_depthMarek Olšák2017-11-071-2/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: limit the scissor bug workaround to Vega10 and Raven onlyMarek Olšák2017-11-071-4/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* etnaviv: Don't over-pad compressed texturesWladimir J. van der Laan2017-11-061-9/+15
| | | | | | | | | HALIGN_FOUR/SIXTEEN has no meaning for compressed textures, and we can't render to them anyway. So use the tightest possible packing. This avoids bugs with non-power-of-two block sizes. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: ASTC texture supportWladimir J. van der Laan2017-11-067-2/+57
| | | | | | | | Add ASTC texture support for hardware that supports this (currently only GC3000 on i.MX6qp is known to have this). Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: Update from rnndbWladimir J. van der Laan2017-11-0613-320/+1015
| | | | | | | Updated as of etnav_viv commit 3b4a8ec. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* radeonsi: enable signed vertex buffer offsetsMarek Olšák2017-11-062-15/+12
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* gallium: add PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSETMarek Olšák2017-11-0616-0/+16
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* radeonsi: don't map big VRAM buffers for the first upload directlyMarek Olšák2017-11-062-0/+21
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/u_threaded: don't map big VRAM buffers for the first upload directlyMarek Olšák2017-11-061-2/+8
| | | | | | | This improves Paraview "many spheres" performance 4x along with the radeonsi commit. Reviewed-by: Nicolai Hähnle <[email protected]>
* nv50,nvc0: Display shared memory usage in pipe_debug_messagePierre Moreau2017-11-042-6/+8
| | | | Signed-off-by: Pierre Moreau <[email protected]>
* nv50,nvc0: Copy shared memory per block to the program info structure and backPierre Moreau2017-11-042-0/+4
| | | | | | | | In OpenCL/CUDA kernels, shared memory usage can be defined within the kernel code. Those usage will only be picked up while parsing the SPIR-V, during the translation phase of the program. Signed-off-by: Pierre Moreau <[email protected]>
* nv50/ir: Store shared memory per block in nv50_ir_prog_infoPierre Moreau2017-11-041-0/+1
| | | | Signed-off-by: Pierre Moreau <[email protected]>
* winsys/amdgpu: Add R600_DEBUG flag to reserve VMID per ctx.Andrey Grodzovsky2017-11-032-0/+2
| | | | | | | | | | Fixes reverted patch f03b7c9 by doing VMID reservation per process and not per context. Also updates required amdgpu libdrm version since the change involved interface updates in amdgpu libdrm. Signed-off-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* i915g: remove some unknown cap warnings.Dave Airlie2017-11-031-0/+8
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* i915g: make gears run again.Dave Airlie2017-11-034-4/+24
| | | | | | | We need to validate some structs exist before we dirty the states, and avoid the problem in some other places. Fixes: e027935a7 ("st/mesa: don't update unrelated states in non-draw calls such as Clear")
* ac/radeonsi: add support for tex instr without a derefenceTimothy Arceri2017-11-031-0/+5
| | | | | | | | | | | These are produced by nir_lower_bitmap(), adding the missing derefence would cause other issues that need to be hacked around such as skipping sampler lowering and uniform location assignment, so this change seems the correct way to go. Fixes 194 piglit crashes on radeonsi using NIR. Reviewed-by: Nicolai Hähnle <[email protected]>
* r600: add support for early depth/stencil.Dave Airlie2017-11-031-0/+3
| | | | | | | | This add support for the early depth/stencil property found on image shaders. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: add support for emitting RAT instructions to the assembler.Dave Airlie2017-11-033-0/+35
| | | | | | | | This adds support for emitting RAT instructions to the assembler. RAT instructions are used to implement image accessors. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: add support for mark bit to the assembler.Dave Airlie2017-11-033-0/+7
| | | | | | | | This adds support to the assembler for the mark bit on the export word1. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: add support for valid pixel mode on CF clausesDave Airlie2017-11-032-0/+2
| | | | | | | | This just adds support to the assembler for setting the valid pixel mode on the CF clause. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: add support for some ALU sources.Dave Airlie2017-11-031-0/+9
| | | | | | | | | | These special ALU sources provide the shader engine, simd and hw wave ids. These are required for images support. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: remove 'Authors:' commentsMarek Olšák2017-11-0235-140/+0
| | | | | | | It's inaccurate. Instead, see the copyright and use "git log" and "git blame" to know the authorship. Acked-by: Nicolai Hähnle <[email protected]>
* etnaviv: Allow clearing constant buffer using buffer==NULL user_buffer==NULLWladimir J. van der Laan2017-11-021-1/+1
| | | | | | | | | Prevents an assertion when using GALLIUM_HUD with ioquake3, when cso_restore_constant_buffer_slot0 restores an empty constant buffer in slot 0. Signed-off-by: Wladimir J. van der Laan <[email protected]> Signed-off-by: Lucas Stach <[email protected]>
* etnaviv: Don't flush on transfer when UNSYNCHRONIZEDWladimir J. van der Laan2017-11-021-12/+12
| | | | | | | | | Structure code to only flush when we will potentially call cpu_prep. This prevents spurious flushes in applications that heavily rely on u_uploader. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Signed-off-by: Lucas Stach <[email protected]>
* etnaviv: don't do resolve-in-place without valid TSWladimir J. van der Laan2017-11-024-0/+11
| | | | | | | | | | | | GC3000 resolve-in-place assumes that the TS state is configured. If it is not, this will result in MMU errors. This is especially apparent when using glGenMipmaps(). Fixes: 78ade659569e ("etnaviv: Do GC3000 resolve-in-place when possible") Cc: [email protected] Signed-off-by: Wladimir J. van der Laan <[email protected]> Tested-by: Chris Healy <[email protected]> Signed-off-by: Lucas Stach <[email protected]>
* svga: Use __asm__ instead of asmDylan Baker2017-11-012-8/+5
| | | | | | | | | | | | __asm__ is portable, and allows the svga driver to be compiled with the c99 standard instead of requiring the gnu99 standard. I have compile tested this with GCC and Clang on Linux. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Brian Paul <[email protected]> Tested-by: Brian Paul <[email protected]>
* Revert "winsys/amdgpu: Add R600_DEBUG flag to reserve VMID per ctx."Marek Olšák2017-11-012-2/+0
| | | | | | This reverts commit f03b7c9ad92c1656a221297819fbc6d065cc0af7. The libdrm interface is wrong.
* gallium: add cap for driver specified max combined shader resources.Dave Airlie2017-11-0116-0/+16
| | | | | | | | Some hw (evergreen) has a limit on how many combined (images/buffers/mrts) a fragment shader can access. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/sb: bail out if prepare_alu_group() doesn't find a proper schedulingGert Wollny2017-11-012-20/+31
| | | | | | | | | | | | | | | It is possible that the optimizer ends up in an infinite loop in post_scheduler::schedule_alu(), because post_scheduler::prepare_alu_group() does not find a proper scheduling. This can be deducted from pending.count() being larger than zero and not getting smaller. This patch works around this problem by signalling this failure so that the optimizers bails out and the un-optimized shader is used. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103142 Cc: <[email protected]> Signed-off-by: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: fix culldist_writemask in nir pathTimothy Arceri2017-11-011-2/+1
| | | | | | | | | | | | The shared si_create_shader_selector() code already offsets the mask. Fixes the following piglit tests: arb_cull_distance/clip-cull-3.shader_test arb_cull_distance/clip-cull-4.shader_test Fixes: 29d7bdd179bb (radeonsi: scan NIR shaders to obtain required info) Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: Add R600_DEBUG flag to reserve VMID per ctx.Andrey Grodzovsky2017-10-312-0/+2
| | | | | Signed-off-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* broadcom/vc5: Force blending to treat alpha as 1 for formats without alpha.Eric Anholt2017-10-303-7/+27
| | | | | | | Fixes fbo-blending-formats on RGB8 and 565. We will still need to demote blending to shader code in the MRT case to fix it in general, but that can be added when we start doing 32F blending (which also needs to be done in the shader).
* broadcom/vc5: Do BGRA vs RGBA swapping for the BLEND_CONSTANT_COLOR.Eric Anholt2017-10-304-11/+30
| | | | Fixes many of the fbo-blending-formats tests.
* broadcom/vc5: Pack clear colors according to the TLB internal format/type.Eric Anholt2017-10-302-10/+49
| | | | | | | | | | The previous packing I did got us all the R*16F and R*32F formats, where the pipe format basically matched the TLB's format, but since the clear color will just be memcpyed to the TLB, we should be looking at its format for deciding how to pack. Fixes RGB565, RGB5_A1 and RGBA10 fbo-clear-formats tests and improves 4444.
* broadcom/vc5: Don't do r/b channel swapping on 565.Eric Anholt2017-10-301-1/+7
| | | | The HW's format actually matches the gallium format.
* broadcom/vc5: Use the proper gallium format for our RGB10_A2.Eric Anholt2017-10-301-1/+1
| | | | This keeps us from needing our own reswizzling of the B vs R fields.
* broadcom/vc5: Drop duplicated setup of clip_window_height_in_pixels.Eric Anholt2017-10-301-1/+0
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* broadcom/vc5: Don't forget to actually turn on stencil testing.Eric Anholt2017-10-301-0/+3
| | | | | I had the rest of stencil state set up, but forgot to actually enable it in the higher level configuration bits packet.
* broadcom/vc5: Set up MSAA texture type according to the internal format.Eric Anholt2017-10-302-2/+39
| | | | | It gets most of EXT_framebuffer_multisample-formats passing, but doesn't really work for texture views.
* broadcom/vc5: Use the sampler view's format, not the resource's.Eric Anholt2017-10-303-8/+1
| | | | | This should help with texture views, though I just noticed this while reading the code.
* broadcom/vc5: Emit raw loads for MSAA buffers.Eric Anholt2017-10-301-0/+58
| | | | | Similar to stores, but we also need to emit dummy stores in between each load, to flush out the previous queued load.
* broadcom/vc5: Use raw stores for MSAA buffers.Eric Anholt2017-10-301-15/+97
| | | | | | | | | | | We were storing the resolved pixels in all cases, but nr_samples > 0 means we should be keeping the per-sample values. We will probably want to change the job structure at some point, as we'll want to recognize full-buffer resolves and do the resolved store in the same job as the original rendering, meaning we'll need to track both the MSAA and single-sample resources in the job. However, this will be enough to build the rest of the MSAA support.
* broadcom/vc5: Add lowering for txf_ms to a txf on a 2x2-scaled texture.Eric Anholt2017-10-301-2/+0
| | | | | | | | | The HW has no native sampler support for multisample textures, but since we only need to support txf_ms and the layout is UIF, we just need to scale up the texcoords and then add in the sample. This drops the old TEXTURE_MSAA_ADDR special uniform, since we're treating MSAA textures as textures, rather than basically texbos like VC4 had to.
* broadcom/vc5: Lay out MSAA textures/renderbuffers as UIF scaled by 4.Eric Anholt2017-10-302-14/+37
| | | | | | We just need to multiply width/height by 2 each, and always set them up as UIF tiling, since that's how the TLB will store them in raw (per-sample) mode.
* broadcom/vc5: Add PIPE_TEX_WRAP_CLAMP support for linear-filtered textures.Eric Anholt2017-10-301-2/+6
| | | | | | I already had the texture's wrapping set up to use different behavior for nearest or linear, so we just needed to saturate the coordinates in linear mode to get the "proper" blend between the edge and border values.
* broadcom/vc5: Disable GL_ARB_transform_feedback3.Eric Anholt2017-10-301-1/+1
| | | | We don't seem to have a way to generally handle gl_SkipComponents.
* broadcom/vc5: Fix gl_FragCoord pixel center setup.Eric Anholt2017-10-301-3/+4
| | | | Fixes glsl-arb-fragment-coord-conventions.
* broadcom/vc5: Always set up 1D textures as raster order.Eric Anholt2017-10-301-0/+5
| | | | | | 1D is the exception to "all V3D textures are tiled", since tiling 1D textures would just waste memory and cache space. This ended up being a problem once we started actually marking 1D textures as 1D instead of 2D.
* broadcom/vc5: Fix GPU hang with no vertex elements used by the VS.Eric Anholt2017-10-301-4/+24
| | | | | | Like VC4, we need to at least have one element set up, but unlike VC4 it seems we don't need to read it to keep the HW happy. Fixes GPU hangs with glsl-no-vertex-attribs.shader_test.
* etnaviv: add ext_texture_srgb supportChristian Gmeiner2017-10-283-1/+10
| | | | | | | | | | | | | | Following piglits are passing: - glean@texture_srgb - spec@ext_texture_srgb@fbo-srgb - spec@ext_texture_srgb@tex-srgb - spec@ext_texture_srgb@texwrap formats - spec@ext_texture_srgb@texwrap formats-s3tc Btw. this enables GL 2.1 :-) Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]>
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