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* gallium: add a cap to expose whether driver supports mixed color/zs bitsIlia Mirkin2016-08-2315-0/+15
| | | | | | | | | | Some hardware can't render to color/depth buffers of mixed bitness. When that happens a fallback has to happen, but this allows the driver to express that this isn't an optimal scenario. The purpose of this is to remove such fbconfigs from the GLX/EGL config list. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nv50/ir: make sure cfg iterator always hits all blocksIlia Mirkin2016-08-231-4/+4
| | | | | | | | | | | | In some very specially-crafted cases, we could attempt to visit a node that has already been visited, and then run out of bb's to visit, while there were still cross blocks on the list. Make sure that those get moved over in that case. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96274 Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Cc: [email protected]
* vc4: Tell state_tracker that we would prefer NIR.Eric Anholt2016-08-223-8/+31
| | | | | | | | | | Before this series, the code generation path was: GLSL IR -> TGSI -> NIR -> NIR clone -> QIR -> QPU Now it's (generally) GLSL IR -> NIR -> NIR clone -> QIR -> QPU
* vc4: Use proper type sizes for uniforms.Eric Anholt2016-08-221-4/+5
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* vc4: Add VARYING_SLOT_PNTC support.Eric Anholt2016-08-221-4/+5
| | | | We end up with this when doing GLSL-to-NIR.
* vc4: Fix vc4_nir_lower_io for non-vec4 I/O.Eric Anholt2016-08-221-22/+12
| | | | | To support GLSL-to-NIR, we need to be able to support actual float/vec2/vec3 varyings.
* nir: Define system values for vc4's blending-lowering arguments.Eric Anholt2016-08-224-46/+54
| | | | | | | | | | | | | In the GLSL-to-NIR conversion of VC4, I had a bit of trouble with what I was calling the "state uniforms" that I was putting into the NIR fighting with its other lowering passes. Instead of using magic uniform base numbers in the backend, follow the lead of load_user_clip_plane and just define system values for them. v2: Fix unintended change to channel_num, drop unspecified const_index value on blend_const_color_r_float. Reviewed-by: Kenneth Graunke <[email protected]>
* llvmpipe: fix issues with depth clampRoland Scheidegger2016-08-203-49/+94
| | | | | | | | | | | | | | | | We only did depth clamp when the value was written from the fs. This is very wrong both for d3d10 and GL, and only passed the corresponding piglit test due to pure luck (it no longer does with the enhanced test). Also, interpolation clamped values to 1.0 always, which can legitimately happen if depth clip is disabled, so fix that as well (untested). There is one unresolved issue left, d3d10 always does depth clamping, whereas GL does not (but does [0,1] clamp instead for fs depth outputs) - this information isn't in any gallium state object, leave it as-is for now (though it looks like llvmpipe misses the [0,1] clamp as well). This (with the previous patch) fixes piglit depth-clamp-range test. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: fix depth clamping wrt reversed near/far valuesRoland Scheidegger2016-08-201-9/+3
| | | | | | | | | | | This wasn't handled before (the result was that no matter what value got clamped, it always ended up as the near value in this case) (if clamping actually happened). Fix this by using the util helper for that (the math is otherwise "mostly" the same, mostly because there could actually be differences due to float rounding, but I don't even know which one would be more correct). Reviewed-by: Jose Fonseca <[email protected]>
* a4xx: make sure to actually clamp depth as requestedIlia Mirkin2016-08-192-2/+29
| | | | | | | | | | | We were previously ... not clamping. I guess this meant that everything got clamped to 1/0, which was enough to pass the existing tests. Or perhaps the clamping would only happen to the rasterized depth value and not the frag shader's output depth value. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97231 Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* a4xx: only disable depth clipping, not all clipping, when requestedIlia Mirkin2016-08-192-1/+4
| | | | | | | | | | The previous bit disables the whole clipper, including the regular viewport-related clipping that would go on. The two new bits disable near and far clipping (separately, as verified with the depth-clamp-range piglit). Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* vc4: Switch store_output to using nir_lower_io_to_scalar / component.Eric Anholt2016-08-192-44/+16
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* vc4: Use the intrinsic's first_component for vattr VPM index.Eric Anholt2016-08-192-7/+3
| | | | Avoids another multiplication by 4 of the base in the NIR.
* vc4: Convert to using nir_lower_io_scalar for FS inputs.Eric Anholt2016-08-192-44/+62
| | | | | The scalarizing of FS inputs can be done in a non-driver-dependent manner, so extract it out of the driver.
* vc4: Switch to using the intrinsic accessors.Eric Anholt2016-08-193-23/+29
| | | | | The const_index[] values have always felt magic, and this documents them a bit better.
* ttn: Use nir_load_front_face instead of the TGSI-style input.Eric Anholt2016-08-192-60/+1
| | | | | | | This reduces the diff between GLSL-to-NIR and TGSI-to-NIR, and gives NIR more optimization to work on. Reviewed-by: Kenneth Graunke <[email protected]>
* ttn: Make FRAG_RESULT_DEPTH be a float variable to match gtn and ptn.Eric Anholt2016-08-193-8/+1
| | | | | | | This lets TTN-using drivers handle FRAG_RESULT_DEPTH the same between all their source paths. Reviewed-by: Rob Clark <[email protected]>
* vc4: Dump the TGSI before trying to convert it to NIR.Eric Anholt2016-08-191-4/+3
| | | | In the case of debugging a crash in TTN, this is nice to have.
* radeon/vce: set flag based on dual instance enablementBoyuan Zhang2016-08-191-2/+4
| | | | | | | Set the flag on when dual instance encoding is supported, otherwise set it to off. Signed-off-by: Boyuan Zhang <[email protected]>
* radeonsi: initialize and finalize the LLVM function pass managerMarek Olšák2016-08-181-0/+2
| | | | Reviewed-by: Tom Stellard <[email protected]>
* swr: [rasterizer core] only use Viewport/Scissors during SwrDraw* operationsTim Rowley2016-08-1712-415/+400
| | | | | | | | | | | Add explicit rects for: - SwrClearRenderTarget - SwrDiscardRect - SwrInvalidateTiles - SwrStoreTiles Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer common] reorder SWR_FORMAT_INFOTim Rowley2016-08-172-825/+1433
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] make dirtytile list point directly to macrotilequeuesTim Rowley2016-08-173-14/+15
| | | | | | Speeds up high geometry HPC workloads. Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] portability - remove use of INT64Tim Rowley2016-08-171-2/+2
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] viewport transform disabled fixTim Rowley2016-08-171-4/+11
| | | | | | | When viewport transform is disabled (ie. screen space coords are passed in directly), the W component should be interpreted as RHW. Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] clamp scissor rects to current tile rectTim Rowley2016-08-171-0/+18
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] align stats structuresTim Rowley2016-08-171-2/+2
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] use AVX2 permute to simplify PaTriListTim Rowley2016-08-171-1/+35
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] move some global variables to SWR_CONTEXTTim Rowley2016-08-172-9/+9
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] change scale on VP matrix element gathersTim Rowley2016-08-171-6/+6
| | | | | | | Was 1, which led to pulling denorms for non-zero indices. Changed to sizeof(float). Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer] implementing native AVX-512 simd16 intrinsicsTim Rowley2016-08-172-84/+265
| | | | Signed-off-by: Tim Rowley <[email protected]>
* svga: fix src/dst typo in can_blit_via_copy_region_vgpu10()Brian Paul2016-08-171-1/+1
| | | | | | | | | | The function was always returning false because of this typo. Retested with piglit. There's some sRGB-related blit failures, but that seems unrelated. Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: Neha Bhende <[email protected]>
* svga: initialize a variable to silence a gcc warningBrian Paul2016-08-171-1/+1
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* radeonsi: fix up buffer descriptor upper-bound checkingMarek Olšák2016-08-171-1/+1
| | | | | | st/mesa does this too, so we're safe. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: change pipe_image_view::first_element/last_element -> offset/sizeMarek Olšák2016-08-175-36/+18
| | | | | | | | | This is required by OpenGL. Our hardware supports this. Example: Bind RGBA32F with offset = 4 bytes. Acked-by: Ilia Mirkin <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* gallium: change pipe_sampler_view::first_element/last_element -> offset/sizeMarek Olšák2016-08-1719-65/+68
| | | | | | | | | | | This is required by OpenGL. Our hardware supports this. Example: Bind RGBA32F with offset = 4 bytes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97305 Acked-by: Ilia Mirkin <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: assign the highest priority to scratch; make rings secondMarek Olšák2016-08-172-4/+6
| | | | | | | just FYI, the kernel receives priority/4 Acked-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/winsys: re-number winsys priority flagsMarek Olšák2016-08-171-16/+13
| | | | | | | free 60..63, move CP_DMA up Acked-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: mark shader rings as highest-priority buffersMarek Olšák2016-08-175-7/+7
| | | | | | | and rename the enum Acked-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: set SHADER_RW_BUFFER priority for streamout buffersMarek Olšák2016-08-172-4/+6
| | | | | Acked-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use current context for DCC feedback-loop decompress, fixes ElementalMarek Olšák2016-08-174-16/+38
| | | | | | | | | | This is just a workaround. The problem is described in the code. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96541 v2: say that it's only between the current context and aux_context Reviewed-by: Nicolai Hähnle <[email protected]> (v1)
* radeonsi: simplify CB_TARGET_MASK logicMarek Olšák2016-08-171-14/+7
| | | | | | we can now rely on CB_COLORn_INFO to disable empty slots. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't set CB_COLOR1_INFO for dual src blendingMarek Olšák2016-08-171-7/+0
| | | | | | | | | Vulkan doesn't do this. The reason may be that CB_COLOR1_INFO.SOURCE_FORMAT from NI was moved to SPI_SHADER_COL_FORMAT for SI. I asked CB guys about this 2 days ago and they still haven't replied. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: eliminate PS OUT[1] if dual src blending is off and CB1 is not boundMarek Olšák2016-08-172-11/+7
| | | | | | All VP DX9 ports benefit from this. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: use unflushed fences for PIPE_QUERY_GPU_FINISHEDMarek Olšák2016-08-171-2/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: use lp_build_alloca_undefNicolai Hähnle2016-08-171-13/+4
| | | | | | | | Avoid building all those store 0 / store undef instruction pairs that end up getting removed anyway. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: protect against out of bounds temporary array accessesNicolai Hähnle2016-08-171-0/+15
| | | | | | | They can lead to VM faults and worse, which goes against the GL robustness promises. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: add radeon_llvm_bound_index for bounds checkingNicolai Hähnle2016-08-173-18/+34
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: reduce alloca of temporaries based on usagemaskNicolai Hähnle2016-08-172-10/+54
| | | | | | v2: take actual writemasks into account Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: use tgsi_scan_arrays for temp arraysNicolai Hähnle2016-08-173-5/+10
| | | | Reviewed-by: Marek Olšák <[email protected]>
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