| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | radeon/llvm: Remove AMDIL GLOBALSTORE* instructions | Tom Stellard | 2012-06-01 | 4 | -77/+36 |
| * | radeon/llvm: Remove AMDIL GLOBALLOAD* instructions | Tom Stellard | 2012-06-01 | 6 | -128/+24 |
| * | r600g: compute support for evergreen | Adam Rak | 2012-06-01 | 20 | -12/+2674 |
| * | svga: fix saturated TEX instructions | Brian Paul | 2012-05-31 | 1 | -6/+13 |
| * | draw: simplify index buffer specification | Brian Paul | 2012-05-31 | 9 | -28/+28 |
| * | nv50: hook up forgotten short constant buffer upload method | Marcin Slusarz | 2012-05-29 | 1 | -0/+1 |
| * | radeon/llvm: Update and fix some comments | Tom Stellard | 2012-05-29 | 2 | -12/+6 |
| * | radeonsi: Remove use.sgpr* intrinsics, use load instructions instead | Tom Stellard | 2012-05-29 | 5 | -74/+57 |
| * | radeonsi: Handle TGSI CONST registers | Tom Stellard | 2012-05-29 | 12 | -100/+254 |
| * | radeon/llvm: Remove AMDILIntrinsicInfo::GetDeclaration fuction body | Tom Stellard | 2012-05-29 | 1 | -20/+1 |
| * | radeon/llvm: Remove AMDILTargetMachine | Tom Stellard | 2012-05-29 | 19 | -363/+90 |
| * | nouveau: unreference fences on resource destruction | Christoph Bumiller | 2012-05-29 | 2 | -0/+6 |
| * | nvc0: optimize blend cso by checking which by-RT data actually differs | Christoph Bumiller | 2012-05-29 | 1 | -65/+94 |
| * | nvc0: don't upload UCPs if the shader doesn't use them | Christoph Bumiller | 2012-05-29 | 1 | -1/+1 |
| * | nvc0/ir: allow 64-bit constant loads on nve4 | Christoph Bumiller | 2012-05-29 | 2 | -1/+3 |
| * | nvc0/ir: fix texture barrier insertion to prevent WAW hazards | Christoph Bumiller | 2012-05-29 | 6 | -29/+88 |
| * | nvc0/ir: TEX doesn't support JOIN modifier either | Christoph Bumiller | 2012-05-29 | 1 | -0/+1 |
| * | nv30: Fix generic passing to fragment program in NV34. | Roy Spliet | 2012-05-25 | 3 | -5/+9 |
| * | nv30: handle user index buffers | Christoph Bumiller | 2012-05-25 | 4 | -17/+27 |
| * | radeon/llvm: Use a custom inserter for MASK_WRITE | Tom Stellard | 2012-05-25 | 4 | -34/+36 |
| * | radeon/llvm: Use tablegen pattern to lower bitconvert | Tom Stellard | 2012-05-25 | 4 | -294/+11 |
| * | radeon/llvm: Use a custom inserter to lower FNEG | Tom Stellard | 2012-05-25 | 5 | -22/+15 |
| * | radeon/llvm: Use a custom inserter to lower CLAMP | Tom Stellard | 2012-05-25 | 9 | -84/+41 |
| * | radeon/llvm: Use a custom inserter to lower FABS | Tom Stellard | 2012-05-25 | 10 | -42/+41 |
| * | r600g: handle R16G16B16_FLOAT and R32G32B32_FLOAT in translate_colorswap | Kai Wasserbäch | 2012-05-25 | 1 | -0/+2 |
| * | svga: remove the special zero-stride vertex array code | Brian Paul | 2012-05-25 | 9 | -153/+12 |
| * | Revert "r600g: set round_mode to truncate and get rid of tgsi_f2i on evergreen" | Vadim Girlin | 2012-05-25 | 2 | -6/+56 |
| * | radeon/llvm: add FLT_TO_UINT, UINT_TO_FLT instructions | Vadim Girlin | 2012-05-25 | 1 | -0/+20 |
| * | radeon/llvm: prepare to revert the round mode state to default | Vadim Girlin | 2012-05-25 | 1 | -2/+9 |
| * | radeon/llvm: fix sampler index in llvm_emit_tex | Vadim Girlin | 2012-05-25 | 1 | -2/+4 |
| * | radeon/llvm: fix opcode for RECIP_UINT_r600 | Vadim Girlin | 2012-05-25 | 1 | -1/+1 |
| * | radeon/llvm/loader: convert hardcoded gpu name to option | Vadim Girlin | 2012-05-25 | 1 | -2/+3 |
| * | r600g: add RECIP_INT, PRED_SETE_INT to r600_bytecode_get_num_operands | Vadim Girlin | 2012-05-25 | 1 | -0/+2 |
| * | i915g: Check for geometry shader earlier in i915_set_constant_buffer. | Vinson Lee | 2012-05-24 | 1 | -4/+4 |
| * | radeon/llvm: Lower UDIV using the Selection DAG | Tom Stellard | 2012-05-24 | 8 | -212/+126 |
| * | radeon/llvm: Remove auto-generated AMDIL->ISA conversion code | Tom Stellard | 2012-05-24 | 14 | -280/+28 |
| * | radeon/llvm: Remove AMDIL instructions MULHI, SMUL | Tom Stellard | 2012-05-24 | 3 | -10/+5 |
| * | radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR) | Tom Stellard | 2012-05-24 | 8 | -693/+6 |
| * | radeon/llvm: Remove AMDIL FTOI and ITOF instructions | Tom Stellard | 2012-05-24 | 7 | -316/+7 |
| * | radeon/llvm: Remove AMDIL EXP* instructions | Tom Stellard | 2012-05-24 | 5 | -15/+7 |
| * | radeon/llvm: Remove AMDIL ADD instructions | Tom Stellard | 2012-05-24 | 6 | -179/+4 |
| * | radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT) | Tom Stellard | 2012-05-24 | 8 | -422/+8 |
| * | radeon/llvm: Remove AMDILMachinePeephole pass | Tom Stellard | 2012-05-24 | 4 | -177/+0 |
| * | radeon/llvm: Remove AMDIL CMP instructions and associated lowering code | Tom Stellard | 2012-05-24 | 3 | -661/+22 |
| * | radeon/llvm: Remove AMDIL ROUND_NEAREST instruction | Tom Stellard | 2012-05-24 | 4 | -6/+6 |
| * | radeon/llvm: Remove AMDIL ROUND_POSINF instruction | Tom Stellard | 2012-05-24 | 4 | -6/+10 |
| * | radeon/llvm: Add custom SDNode for FRACT | Tom Stellard | 2012-05-24 | 6 | -6/+10 |
| * | radeon/llvm: Use -1 as true value for SET* integer instructions | Tom Stellard | 2012-05-24 | 3 | -32/+28 |
| * | radeon/llvm: Handle SETGE_INT, SETGE_UINT, and SETGT_UINT opcodes | Tom Stellard | 2012-05-24 | 1 | -0/+6 |
| * | radeon/llvm: Avoid error with SI in EmitInstrWithCustomInserter() | Tom Stellard | 2012-05-24 | 1 | -0/+1 |
