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* svga: replace gotos with else clausesBrian Paul2018-02-153-23/+20
| | | | | | Simple clean-up. Reviewed-by: Charmaine Lee <[email protected]>
* svga: s/unsigned/enum pipe_shader_type/Brian Paul2018-02-153-4/+6
| | | | Reviewed-by: Neha Bhende <[email protected]>
* svga: move duplicated code for setting fillmode/flatshade stateBrian Paul2018-02-151-20/+10
| | | | | | | Move the calls to svga_hwtnl_set_fillmode() and svga_hwtnl_set_flatshade() out of the two retry_draw_*() functions to the svga_draw_vbo() function. Reviewed-by: Charmaine Lee <[email protected]>
* svga: move svga_update_state() call in draw codeBrian Paul2018-02-151-18/+19
| | | | | | | | | | | | | | | | This fixes a few Piglit transform feedback regressions caused by commit 7a1401938b351. In that change I moved the moved svga_update_state() into the loops, after the calls to svga_hwtnl_set_flatshade(). But svga_hwtnl_set_flatshade() actually depends on some derived shader state. This patch moves the svga_update_state() call into svga_draw_vbo() so it's not duplicated in two places. Fixes: 7a1401938b351 ("svga: clean up retry_draw_range_elements(), retry_draw_arrays()") Reviewed-by: Charmaine Lee <[email protected]>
* svga: call tgsi_scan_shader() for dummy shadersBrian Paul2018-02-152-0/+7
| | | | | | | | | | | | | | If we fail to compile the normal VS or FS we fall back to a simple/ dummy shader. We need to rescan the the shader to update the shader info. Otherwise, this can lead to further translations failures because the shader info doesn't match the actual shader. Found by adding some extra debug assertions in the state-update code while debugging something else. v2: also update shader generic_inputs/outputs, etc. per Charmaine Reviewed-by: Charmaine Lee <[email protected]>
* nvc0: disable MS Images for sample_count == 1 on MaxwellKarol Herbst2018-02-151-1/+1
| | | | | | | | fixes KHR-GL45.multi_bind.dispatch_bind_textures on Maxwell Suggested-by: Ilia Mirkin <[email protected]> Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* radeonsi/nir: fix si_nir_load_tcs_varyings() for outputsTimothy Arceri2018-02-151-2/+11
| | | | | | We were incorrectly using the input info for outputs. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: fix shader ballot return value bitsizeTimothy Arceri2018-02-151-1/+1
| | | | | | | Fixes cts test: KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot Reviewed-by: Marek Olšák <[email protected]>
* ac: remove nir_to_llvm_context from ac_nir_translate()Samuel Pitoiset2018-02-141-1/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* r600: fix regression in gl_FragColor drawingDave Airlie2018-02-141-0/+2
| | | | | | | This fixes a regression in the broadcast color to all color bufs case. Fixes: 6c691081a (r600: fixup sparse color exports.) Signed-off-by: Dave Airlie <[email protected]>
* r600: fix array spill if temp[0] is before all arraysDave Airlie2018-02-141-0/+2
| | | | | | | | | | | | | | | | I found a shader with DCL TEMP[0], LOCAL DCL TEMP[1..256], ARRAY(1), LOCAL DCL TEMP[257..512], ARRAY(2), LOCAL DCL TEMP[513..768], ARRAY(3), LOCAL DCL TEMP[769], LOCAL This would remap badly, as it would add up all the spilled sizes and subtract it from the temp for 0. If the current temp is less than the array start break out. Fixes: 1d871aa6 (r600g: Implement spilling of temp arrays (v2)) Signed-off-by: Dave Airlie <[email protected]>
* virgl: add ARB_sample_shading support.Dave Airlie2018-02-143-3/+6
| | | | | | This enable ARB_sample_shading if the renderer supports it. Signed-off-by: Dave Airlie <[email protected]>
* virgl: add ARB_draw_indirect support.Dave Airlie2018-02-143-2/+28
| | | | | | This relies on the renderer code landing first. Signed-off-by: Dave Airlie <[email protected]>
* gallium: drop all the guard band float caps.Dave Airlie2018-02-1414-72/+0
| | | | | | | | | | Nobody queries these and nobody sets them to anything useful, the docs say TODO. Drop them until a use appears. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* virgl: Support v2 caps struct (v2)Stéphane Marchesin2018-02-132-12/+45
| | | | | | | | | This struct allows us to report: - accurate max point size/line width. - accurate texel and texture gather offsets - vertex/geometry limits. Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: make si_declare_compute_memory() more generic and call for nirTimothy Arceri2018-02-134-7/+18
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ac: remove unused parameters in abi::load_tess_coord()Samuel Pitoiset2018-02-121-4/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: add load_sample_mask_in() to the ABISamuel Pitoiset2018-02-121-0/+6
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* freedreno: small fix for flushing dependent batchesRob Clark2018-02-101-0/+13
| | | | | | | | | | | | | | | Flush a resource's previous write_batch synchronously. Because a resource's associated batches are not updated until after the flush thread submits rendering to the kernel, this was causing a bit of confusion in the following loop. This fixes a bug that appeared with recent stk. Perhaps we need to re-work things a bit to clear out dependent patches in the ctx's thread and use a fence to deal with the period between when a flush is queued and when it is submitted to the kernel. But this will do until time permits a larger refactor. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: intra-block schedulingRob Clark2018-02-101-22/+104
| | | | | | | | | | | | Because of loops, we can't schedule all of a block's predecessors first. Instead just assume that the result consumed in a block was written far enough away in all paths into a block. And do an intra-block scheduling pass to figure out if there are any cases where we need to insert extra nop's. This works out better than always assuming the worst case (ie. that a value live into a block was written in the last instruction in the predecessor block). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: "boost" the depth of if/else conditionRob Clark2018-02-101-5/+6
| | | | | | | Account for the move to predicate register, to try to avoid needing to insert extra NOPs later. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: account for arrays in delayslot calcRob Clark2018-02-101-2/+30
| | | | | | | | | | | | | Normally false-deps are not something to consider, since they mostly exist for delay-slot related reasons: * barriers * ordering writes after read * SSBO/image access ordering The exception is a false-dependency on an array store. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: more clever legalize algorithmRob Clark2018-02-101-42/+96
| | | | | | | | | | | | | | Previously we didn't handle flow control in legalize, and instead just set (ss)(sy) on the first instruction in every block. Which isn't very clever. Instead, consider output state of all predecessor blocks, so we only set a sync bit if needed for any possible path leading into a block. Because of loops, we can't require that all successor blocks are legalized before a given block, so instead run in a loop until results converge. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: track block predecessorsRob Clark2018-02-102-7/+25
| | | | | | Useful in the following patches. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: clean up dangling false-dep'sRob Clark2018-02-102-0/+46
| | | | | | | | | | | | | Maybe there is a better way for this.. where it comes useful is "array" loads, which end up as a false-dep for a later array store. If all the uses of an array load are CP'd into their consumer, it still leaves the dangling array load, leading to funny things like: mov.u32u32 r5.y, r0.y mov.u32u32 r5.y, r0.z Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle IMMED for mad 2nd src special caseRob Clark2018-02-101-2/+4
| | | | | | | Consider also immediates for swapping the first two srcs, because they can be lowered to constant. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove ir3 phi instructionRob Clark2018-02-108-205/+16
| | | | | | Now that we convert phi webs to ssa, we can drop all this. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove lower_if_else passRob Clark2018-02-104-328/+0
| | | | | | Now that it is unused. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add experimental GCM passRob Clark2018-02-101-0/+7
| | | | | | | | | | Generally seems to do worse on instruction count and register usage, according to shader-db. But shader-db also doesn't do a very good job of weighting loop bodies, so that might not be totally valid. So add an env variable to enable GCM pass for easier experimentation. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: change opt passesRob Clark2018-02-101-0/+14
| | | | | | | There are more useful nir passes added since initial conversion to nir. But ir3 was never updated to use them. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use peephole select passRob Clark2018-02-101-1/+1
| | | | | | | | | | | | | | | Agressively lowering all if/else to selects in some extreme cases results in much higher register pressure. Using peephole select instead with a modest threshold speeds up alu2 4x! 16 seems like a good limit, low enough to help alu2 but not too low that it penalizes everything else. With a bit better scheduling of the instruction that moves a value into a predicate register, we might be able to lower this limit a bit more in the future, but since we need 6 cycles from the move to predicate register to predicated branch, that puts some sort of lower bound on how far we can lower this threshold. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: lower phi webs to regsRob Clark2018-02-101-2/+1
| | | | | | | | | | nir's from_ssa pass is much better at avoiding inserting extra moves than our logic is. And lowering phi webs to regs just treats anything involved in a phi web as an array of length=1. Which with previous array related fixes in RA/etc ends up working out quite well. This cuts down on extra instructions and also helps with register pressure. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: separate arrays from groupsRob Clark2018-02-101-0/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: make block/instruction serialno per-shaderRob Clark2018-02-102-4/+6
| | | | | | | Makes it easier to compare values seen in-game (where there are many shaders) to cmdline standalone compiler. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add spirv support to cmdline compilerRob Clark2018-02-101-3/+60
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't lower fsatRob Clark2018-02-103-1/+23
| | | | | | | | Instead, if possible fold (sat) flag into src, otherwise use: (sat)max.f rD, rS, rS Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add encoding/decoding for (sat) bitRob Clark2018-02-104-12/+42
| | | | | | | | Seems to be there since a3xx, but we always lowered fsat. But we can shave some instructions, especially in shaders that use lots of clamp(foo, 0.0, 1.0) by not lowering fsat. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: extend liverange of arraysRob Clark2018-02-101-0/+11
| | | | | | | Use livein state of other blocks to extend liverange of arrays when they are still needed by successor blocks. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: avoid extra mov's for "arrays"Rob Clark2018-02-101-3/+23
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: a couple more array fixesRob Clark2018-02-101-2/+15
| | | | | | (Plus a couple TODOs) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: keep array storesRob Clark2018-02-101-0/+6
| | | | | | | Since these are not in SSA form, add to block's keeps so it doesn't appear unused. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: propagate barrier informationRob Clark2018-02-101-0/+5
| | | | | | | | When eliminating movs, the instruction that is now directly using the src of the mov has the same scheduling order constraints as the original mov instruction. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove pointless statementRob Clark2018-02-101-3/+0
| | | | | | Function ends after this if/else ladder, so it was pointless. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: some more debug printsRob Clark2018-02-102-0/+36
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix printing of relative branch offsetsRob Clark2018-02-102-3/+3
| | | | | | | | | | | | The number of bits depends on generation. But printing negative values with a5xx encoding (largest size) but compiling for a3xx or a4xx, would result in negative values printed as large positive values. I guess in practice huge negative branch offsets aren't likely (and if that is the case, the shader is probably too big to grok by reading the assembly). So just print using smallest bitfield size. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: be more clever with if/else jumpsRob Clark2018-02-101-1/+16
| | | | | | | | | | | Try to clean up things like: br !p0.x #2 br p0.x #something to eliminate the first branch. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: avoid some spurious sync bitsRob Clark2018-02-101-1/+3
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: print # of sync bits for shaderdbRob Clark2018-02-103-2/+18
| | | | | | When trying to optimize to reduce stalls, it is nice to see this info. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add debug trace for flushRob Clark2018-02-101-0/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* st/radeonsi: enable disk cache for nirTimothy Arceri2018-02-101-4/+0
| | | | Reviewed-by: Marek Olšák <[email protected]>
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