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* radeon/compiler: include stdio.hBrian Paul2015-02-261-0/+1
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89343 Reviewed-by: Tom Stellard <[email protected]>
* r300g: remove dependency on compiler.hBrian Paul2015-02-265-3/+5
| | | | | | | | It only needs typical stdio.h and stdlib.h functions. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* freedreno: drop ARRAY_SIZE macroRob Clark2015-02-251-2/+0
| | | | | | | | | | | | | | | | | Since now ARRAY_SIZE has been added to util/macros.h. Fixes a bunch of: freedreno_util.h:79:0: warning: "ARRAY_SIZE" redefined #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) ^ In file included from ../../../../src/gallium/include/pipe/p_compiler.h:36:0, from ../../../../src/gallium/include/pipe/p_context.h:31, from freedreno_context.h:32, from freedreno_context.c:29: ../../../../src/util/macros.h:29:0: note: this is the location of the previous definition # define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x))) ^ Signed-off-by: Rob Clark <[email protected]>
* r600g,radeonsi: fix streamout after pipeline stats have been usedMarek Olšák2015-02-242-13/+1
| | | | | | | | | | | EVENT_TYPE_PIPELINESTAT_STOP disables streamout queries too. Luckily, pipeline stats are enabled by default, so we don't even have to emit EVENT_TYPE_PIPELINESTAT_START. Tested on Hawaii, Bonaire, Redwood, RV730. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: small cleanup around current_rast_primMarek Olšák2015-02-241-9/+6
| | | | | | | | - remove the last parameter of si_emit_rasterizer_prim_state - remove the last unused parameter of si_emit_draw_registers - use current_rast_prim in si_emit_draw_registers Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: set current_rast_prim in the right placeMarek Olšák2015-02-241-1/+7
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: simplify obtaining a shader property in si_emit_clip_regsMarek Olšák2015-02-241-2/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: only preload VertexID for the GS copy shaderMarek Olšák2015-02-241-4/+6
| | | | | | The copy shader doesn't use any other preloaded VGPRs. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: dump the shader key when dumping shadersMarek Olšák2015-02-241-0/+38
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: cleanup of hex literalsMarek Olšák2015-02-244-32/+32
| | | | | | | | 0x3F800000 -> fui(1.0) 0x00000000 -> 0 Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: set PA_SU_HARDWARE_SCREEN_OFFSET to 0Marek Olšák2015-02-241-0/+2
| | | | | | It was probably 0 already, but it doesn't hurt to set it. Reviewed-by: Michel Dänzer <[email protected]>
* r600g: Implement GL_ARB_draw_indirect for EG/CMGlenn Kennard2015-02-2410-35/+129
| | | | | | | | | | | | | | | | Requires Evergreen/Cayman and radeon kernel module 2.41.0 or newer. Expected piglit fails due to hardware limitations: * arb_draw_indirect-draw-arrays-prim-restart Restarts not applied for DrawArrays commands * arb_draw_indirect-vertexid Base vertex offset is not included in vertex id Marek: bump vgt_state num_dw by 3 (= space needed for one register write) Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* freedreno/a4xx: aniso filteringRob Clark2015-02-241-4/+6
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2015-02-245-5/+20
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: add ARB_instanced_arrays supportRob Clark2015-02-242-5/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: handle index_bias (i.e. base_vertex)Rob Clark2015-02-241-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: add support for vertexid and instanceid sysvalsRob Clark2015-02-242-11/+24
| | | | | | ir3 bits of it already in place from a3xx patch.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: pass number of instances to drawRob Clark2015-02-243-6/+7
| | | | | | | a4xx has it's own draw packet, so needs equivalent update to what a3xx already got. Signed-off-by: Rob Clark <[email protected]>
* vc4: Update to current kernel sources.Eric Anholt2015-02-248-49/+93
| | | | | | New BO create and mmap ioctls are added. The submit ABI gains a flags argument, and the pointers are fixed at 64-bit. Shaders are now fixed at the start of their BOs.
* r600: Fix build after 984f3069370cd4a347cb38269d430b428385affdEric Anholt2015-02-241-1/+1
| | | | | Same as for the CLAMP macro, undef it before including a header file that tries to make fields with that name.
* mesa: Use assert() instead of ASSERT wrapper.Matt Turner2015-02-231-1/+1
| | | | Acked-by: Eric Anholt <[email protected]>
* radeonsi: fix a warning caused by previous commitMarek Olšák2015-02-231-1/+1
| | | | Cc: 10.5 10.4 <[email protected]>
* radeonsi: fix point spritesMarek Olšák2015-02-231-1/+1
| | | | | | | | Broken by a27b74819ad375e8c0bc88e13f42c951d2b5cd6a. This fix is critical and should be ported to stable ASAP. Cc: 10.5 10.4 <[email protected]>
* freedreno/a4xx: set PC_PRIM_VTX_CNTL.VAROUT properlyRob Clark2015-02-211-1/+6
| | | | | | | Fixes xonotic, some webgl stuff, and really pretty much anything with more than 4 varyings. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2015-02-217-16/+44
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: bit of cleanupRob Clark2015-02-214-33/+27
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: implement fenceRob Clark2015-02-214-74/+65
| | | | | | | | | | I never actually implemented the stubbed out fence stuff back in the early days. Fix that. We'll need a few libdrm_freedreno changes to handle timeout properly, so ignore that for now to avoid a libdrm_freedreno dependency bump. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a2xx: fix increment in assertRob Clark2015-02-211-1/+2
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88883 Signed-off-by: Rob Clark <[email protected]>
* ilo: R32G32B32_FLOAT need no special care on Gen8+Chia-I Wu2015-02-211-3/+6
| | | | | Gen8+ must use VALIGN_4. Unlike prior Gens, R32G32B32_FLOAT should supposedly support VALIGN_4.
* ilo: 128 BPP formats can use TiledY on Gen7.5+Chia-I Wu2015-02-211-1/+6
| | | | The restriction is lifted.
* nvc0: enable double supportIlia Mirkin2015-02-201-2/+2
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: remove merge/split pairs to allow normal propagation to occurIlia Mirkin2015-02-201-0/+30
| | | | | | | | | | Because the TGSI interface creates merges for each instruction source and then splits them back out, there are a lot of unnecessary merge/split pairs which do essentially nothing. The various modifier/etc propagation doesn't know how to walk though those, so just remove them when they're unnecessary. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add support for new TGSI double opcodesIlia Mirkin2015-02-201-0/+236
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: handle zero and negative sqrt argumentsIlia Mirkin2015-02-201-2/+14
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: no instruction can load a double immediateIlia Mirkin2015-02-201-0/+2
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: fix lowering of RSQ/RCP/SQRT/MOD to work with F64Ilia Mirkin2015-02-205-16/+40
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gm107/ir: fix F2F flipped stype/dtype flagsIlia Mirkin2015-02-201-2/+2
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gm107/ir: fix DSET boolean float flagIlia Mirkin2015-02-201-0/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gm107/ir: fix DMUL opcode encodingIlia Mirkin2015-02-201-3/+3
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gk110/ir: add emission of dadd/dmul/dmad opcodesIlia Mirkin2015-02-201-3/+77
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmaxIlia Mirkin2015-02-201-3/+63
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gallium/radeon: fix an uninitialized-variable warningMarek Olšák2015-02-201-1/+1
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* gallium: add new double-related shader caps to all the gettersIlia Mirkin2015-02-205-0/+20
| | | | | | | | Missed a few drivers in the earlier changes, this should fix up all the ones that print unknown caps or don't have a default statement. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* svga: add missing _DROUND,DFRACEXP_DLDEXP_SUPPORTED switch casesBrian Paul2015-02-201-0/+2
| | | | To silence unhandled switch case warnings.
* radeonsi: don't use SQC_CACHES to flush ICACHE and KCACHE on SIMarek Olšák2015-02-201-18/+11
| | | | | | | | | | | | | | | This reverts 73c2b0d18c51459697d8ec194ecfc4438c98c139. It doesn't seem to be reliable. It's probably missing a wait packet or something, because it's just a register write and doesn't wait for anything. SURFACE_SYNC at least seems to wait until the flush is done. Just guessing. Let's not complicate things and revert this. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88561 Cc: 10.5 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* vc4: Keep an array of pointers to instructions defining the temps around.Eric Anholt2015-02-198-68/+67
| | | | | The optimization passes are always regenerating it and throwing it away, but it's not hard to keep track of.
* vc4: Move qir_uniform() and the constant-value versions to vc4_qir.c/h.Eric Anholt2015-02-193-45/+49
| | | | | I may want them in optimization passes, and they're not really particular to the program translation stage.
* vc4: Enforce one-uniform-per-instruction after optimization.Eric Anholt2015-02-196-50/+209
| | | | | | | | | | | | | | | This lets us more intelligently decide which uniform values should be put into temporaries, by choosing the most reused values to push to temps first. total uniforms in shared programs: 13457 -> 13433 (-0.18%) uniforms in affected programs: 1524 -> 1500 (-1.57%) total instructions in shared programs: 40198 -> 40019 (-0.45%) instructions in affected programs: 6027 -> 5848 (-2.97%) I noticed this opportunity because with the NIR work, some programs were happening to make different uniform copy propagation choices that significantly increased instruction counts.
* vc4: Rename add_uniform() to qir_uniform().Eric Anholt2015-02-191-15/+15
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* vc4: Shut up runtime warnings about new pipe caps.Eric Anholt2015-02-191-0/+2
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