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* vc4: Fix termination of the initial scan for branch targets.Eric Anholt2016-10-211-11/+8
* radeonsi: fix a regression in si_eliminate_const_outputNicolai Hähnle2016-10-211-4/+3
* nv50,nvc0: don't keep track of whether fb rt0 is integer-onlyIlia Mirkin2016-10-216-44/+22
* nvc0: do not break 3D state by pushing MS coordinates on FermiSamuel Pitoiset2016-10-201-43/+44
* nvc0: translate compute shaders at program creationSamuel Pitoiset2016-10-201-0/+4
* radeonsi: fix build of si_eliminate_const_vs_outputs on LLVM <= 3.8Marek Olšák2016-10-201-3/+2
* radeonsi: fix 64-bit loads from LDSNicolai Hähnle2016-10-201-1/+1
* nv50/ir: process texture offset sources as regular sourcesIlia Mirkin2016-10-191-53/+94
* nv50,nvc0: avoid reading out of bounds when getting bogus so infoIlia Mirkin2016-10-192-2/+8
* nvc0/ir: simplify predicate logic for GK104 atomic operationsSamuel Pitoiset2016-10-191-14/+7
* nvc0/ir: remove useless NVC0LoweringPass::gMemBaseSamuel Pitoiset2016-10-191-4/+1
* nv50/ir: print CCTL subops in debug modeSamuel Pitoiset2016-10-191-0/+9
* radeonsi: eliminate trivial constant VS outputsMarek Olšák2016-10-193-2/+186
* nv50/ir: silent TGSI_PROPERTY_FS_DEPTH_LAYOUTSamuel Pitoiset2016-10-191-0/+1
* radeonsi: remove cb0_is_integer handlingMarek Olšák2016-10-193-13/+3
* svga: minor code improvements in svga_validate_pipe_sampler_view()Brian Paul2016-10-181-8/+8
* radeonsi: rename prefixes from radeon to siMarek Olšák2016-10-184-157/+157
* radeonsi: merge radeon_llvm_context and si_shader_contextMarek Olšák2016-10-184-317/+290
* radeonsi: import all TGSI->LLVM code from gallium/radeonMarek Olšák2016-10-1811-462/+346
* gallium/radeon: simplify initialization of 64-bit gallivm buildersMarek Olšák2016-10-181-18/+4
* gallium/radeon: remove unused radeon_llvm_reg_index_soaMarek Olšák2016-10-182-7/+0
* radeonsi: move LLVM ALU codegen into radeonsiMarek Olšák2016-10-186-992/+1056
* gm107/ir: fix bit offset of tex lod setting for indirect texturingIlia Mirkin2016-10-181-1/+1
* gm107/ir: fix texturing with indirect samplersIlia Mirkin2016-10-181-0/+10
* radeonsi: unify the constant load pathsNicolai Hähnle2016-10-171-28/+11
* radeonsi: fix indirect loads of 64 bit constantsNicolai Hähnle2016-10-171-2/+2
* radeonsi: shorten "shader->selector" to "sel" in si_shader_createMarek Olšák2016-10-171-7/+8
* radeonsi: clear DB_RENDER_OVERRIDEMarek Olšák2016-10-171-3/+1
* vc4: Fix fast clear color packing for 565.Eric Anholt2016-10-161-3/+16
* nv50/ir: constant fold OP_SPLITTobias Klausmann2016-10-141-0/+18
* swr: [rasterizer core] don't construct pArContext on non-ar buildsTim Rowley2016-10-131-0/+6
* swr: [rasterizer core] remove WorkerWaitForThreadEvent bucketTim Rowley2016-10-133-6/+0
* swr: [rasterizer core] move binner functionality to separate fileTim Rowley2016-10-133-1392/+1444
* swr: [rasterizer scripts] add DEBUG_OUTPUT_DIR knobTim Rowley2016-10-131-0/+7
* swr: [rasterizer core] fix comment typoTim Rowley2016-10-131-1/+1
* swr: [rasterizer core/sim] 8x2 backend + 16-wide tile clear/load/storeTim Rowley2016-10-1313-100/+1895
* swr: [rasterizer archrast] fix event file issue with saving dataTim Rowley2016-10-134-8/+22
* swr: [rasterizer common] fix assert indexEric Engestrom2016-10-131-1/+1
* nv50: enable ARB_enhanced_layoutsIlia Mirkin2016-10-131-1/+1
* nvc0/ir: be more careful about preserving modifiers in SHLADD creationIlia Mirkin2016-10-131-7/+5
* vc4: Avoid loading from the texture during non-utile-aligned glTexImage().Eric Anholt2016-10-131-12/+34
* nvc0: enable ARB_enhanced_layoutsSamuel Pitoiset2016-10-131-1/+1
* radeonsi: adjust and clean up Z_ORDER and EXEC_ON_x settingsMarek Olšák2016-10-132-22/+32
* radeonsi: disable ReZMarek Olšák2016-10-131-7/+4
* radeonsi: implement TC-compatible HTILEMarek Olšák2016-10-138-20/+132
* radeonsi: fix regression in image atomicsNicolai Hähnle2016-10-131-1/+1
* radeonsi: fix the coordinate overloading of llvm.amdgcn.image.atomic.cmpswap.*Nicolai Hähnle2016-10-131-2/+7
* swr: automake: add ar_eventhandlerfile_h.template to the tarballEmil Velikov2016-10-121-1/+2
* nvc0/ir: fix textureGather with a single offsetIlia Mirkin2016-10-121-2/+2
* nv50/ir: copy over value's register id when resolving merge of a phiIlia Mirkin2016-10-121-1/+3
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