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* vc4: Fix leaks of the compiled shaders' keys.Eric Anholt2014-12-141-1/+1
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* vc4: Fix leaks of the CL contents.Eric Anholt2014-12-142-1/+6
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* vc4: Fix leak of vc4_bos stashed in the context.Eric Anholt2014-12-141-0/+5
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* vc4: Fix leak of the compiled shader programs in the cache.Eric Anholt2014-12-143-0/+24
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* vc4: Fix leak of a copy of the scheduled QPU instructions.Eric Anholt2014-12-141-2/+3
| | | | They're copied into a vc4_bo after compiling is done.
* vc4: Switch to using the util/ hash table.Eric Anholt2014-12-142-54/+33
| | | | | No performance difference on a microbenchmark with norast that should hit it enough to have mattered, n=220.
* vc4: Fix leak of simulator memory on screen cleanup.Eric Anholt2014-12-142-3/+6
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* vc4: Fix a leak of the simulator's exec BO's actual vc4_bo.Eric Anholt2014-12-141-0/+1
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* util/hash_table: Rework the API to know about hashingJason Ekstrand2014-12-141-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously, the hash_table API required the user to do all of the hashing of keys as it passed them in. Since the hashing function is intrinsically tied to the comparison function, it makes sense for the hash table to know about it. Also, it makes for a somewhat clumsy API as the user is constantly calling hashing functions many of which have long names. This is especially bad when the standard call looks something like _mesa_hash_table_insert(ht, _mesa_pointer_hash(key), key, data); In the above case, there is no reason why the hash table shouldn't do the hashing for you. We leave the option for you to do your own hashing if it's more efficient, but it's no longer needed. Also, if you do do your own hashing, the hash table will assert that your hash matches what it expects out of the hashing function. This should make it harder to mess up your hashing. v2: change to call the old entrypoint "pre_hashed" rather than "with_hash", like cworth's equivalent change upstream (change by anholt, acked-in-general by Jason). Signed-off-by: Jason Ekstrand <[email protected]> Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* freedreno/a4xx: mipmapsRob Clark2014-12-134-24/+80
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-12-135-12/+20
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: add is_a3xx()/is_a4xx() helpersRob Clark2014-12-133-7/+27
| | | | | | | | A bunch of open-coded 'gpu_id > 300's seems like it will eventually cause problems with future generations. There were already a few minor problems with caps for features that still need additional work on a4xx. Signed-off-by: Rob Clark <[email protected]>
* freedreno: helper to calc layer/level offsetRob Clark2014-12-135-21/+31
| | | | | | | Rather than duplicating this everywhere. Especially as on a4xx the layout of layers and levels differs based on texture type. Signed-off-by: Rob Clark <[email protected]>
* gallium: Remove Android files from distribution.Matt Turner2014-12-1210-13/+7
| | | | Android builds Mesa from git, so there don't need to be in the tarball.
* vc4: Fix referencing of sync objects.Eric Anholt2014-12-121-0/+1
| | | | | While the pipe_reference_* helpers set the pointer, a bare pipe_reference doesn't. Fixes 5 ARB_sync tests.
* vc4: Consider FS backface color loads as color inputs as well.Eric Anholt2014-12-111-1/+4
| | | | | This fixes flatshading of backface color in 4 of the piglit interpolation tests.
* vc4: Drop redundant index size setting.Eric Anholt2014-12-111-1/+0
| | | | This is already done at set_index_buffer() time.
* vc4: Don't throw out the index offset in the shadow index buffer path.Eric Anholt2014-12-111-2/+1
| | | | | When we upload shadow indices at draw time, we need the source offset. Fixes the piglit draw-elements test.
* vc4: Fix triangle-guardband-viewport piglit test.Eric Anholt2014-12-111-5/+14
| | | | The original Broadcom driver also did this with the viewport.
* vc4: Fix a memory leak in setting up QPU instructions for scheduling.Eric Anholt2014-12-111-1/+2
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* radeonsi: take into account NULL colorbuffers when computing CB_TARGET_MASKMarek Olšák2014-12-101-4/+12
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: only emit line stippling and provoking vertex state when it changesMarek Olšák2014-12-105-0/+9
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix SPI state dependency on sprite_coord_enableMarek Olšák2014-12-102-2/+4
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix line stippling and provoking vertex state for GS primitivesMarek Olšák2014-12-101-1/+3
| | | | | | I'm not sure if GS hw outputs line lists or line strips. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: emit DRAW_PREAMBLE only if it changesMarek Olšák2014-12-103-8/+17
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove setting of VGT_DISPATCH_DRAW_INDEXMarek Olšák2014-12-101-3/+0
| | | | | | | It's used only if VGT_SHADER_STAGES_EN.DISPATCH_DRAW_EN is 1, which we don't set. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: emit GS_OUT_PRIM_TYPE only if it changesMarek Olšák2014-12-103-1/+6
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: emit primitive restart only if it changesMarek Olšák2014-12-103-5/+22
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: emit base vertex and start instance only if they changeMarek Olšák2014-12-103-3/+38
| | | | | | v2: added a helper function for invalidation of the sh constants Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: emit clip registers only if VS, GS, or rasterizer is changedMarek Olšák2014-12-105-32/+39
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: get info about VS outputs from tgsi_shader_infoMarek Olšák2014-12-103-35/+34
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: move all shader-related functions to a new file si_state_shaders.cMarek Olšák2014-12-106-785/+810
| | | | | | This huge amount of code deserves its own file. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: generate derived and draw-related registers directly in the CSMarek Olšák2014-12-103-75/+76
| | | | | | The big function is split into 3 smaller functions. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: si_conv_pipe_prim shouldn't failMarek Olšák2014-12-101-11/+3
| | | | | | An assertion should suffice. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove useless variable si_context::pm4_dirty_cdwordsMarek Olšák2014-12-103-11/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove unused draw packet functionsMarek Olšák2014-12-102-87/+0
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: emit draw packets directly into the CSMarek Olšák2014-12-103-68/+95
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add emit util functions for SH registersMarek Olšák2014-12-102-1/+18
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r600g: only init GS_VERT_ITEMSIZE on r600Dave Airlie2014-12-101-5/+2
| | | | | | | | | | | | On evergreen there are 4 regs, on r600/700 there is only one. Don't initialise regs and trash someone elses state. Not sure this fixes anything, but hey one less stupid. Reviewed-By: Glenn Kennard <[email protected]> Cc: "10.3 10.4" [email protected] Signed-off-by: Dave Airlie <[email protected]>
* vc4: Do QPU scheduling across uniform loads.Eric Anholt2014-12-091-28/+60
| | | | | | | | This means another pass of reordering the uniform data store, but it lets us pair up a lot more instructions. total instructions in shared programs: 44639 -> 43176 (-3.28%) instructions in affected programs: 36938 -> 35475 (-3.96%)
* vc4: Populate the delay field better, and schedule high delay first.Eric Anholt2014-12-091-1/+49
| | | | | | | This is a standard scheduling heuristic, and clearly helps. total instructions in shared programs: 46418 -> 44467 (-4.20%) instructions in affected programs: 42531 -> 40580 (-4.59%)
* vc4: Skip raddr dependencies for 32-bit immediate loads.Eric Anholt2014-12-091-2/+5
| | | | These don't have raddr fields.
* vc4: Mark VPM read setup as impacting VPM reads, not writes.Eric Anholt2014-12-091-1/+7
| | | | | Fixes assertion failures if we adjust scheduling priorities to emphasize VPM reads more.
* vc4: Refuse to merge instructions involving 32-bit immediate loads.Eric Anholt2014-12-091-0/+5
| | | | | An immediate load overwrites the mul and add operations, so you can't merge with them.
* freedreno/a4xx: frag-coord / face fixesRob Clark2014-12-091-6/+19
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: fix rendering to layer != 0Rob Clark2014-12-091-1/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: temp hack for FLAT varyingsRob Clark2014-12-091-0/+19
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: lower TXP as neededRob Clark2014-12-093-3/+19
| | | | | | On a3xx, lower TXP for 3D textures, on a4xx lower all TXP. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: XA gpu hang at startupRob Clark2014-12-092-1/+9
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: texture fixesRob Clark2014-12-096-7/+54
| | | | Signed-off-by: Rob Clark <[email protected]>
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