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* nv50: assert before trying to out-of-bounds access vtxbufEmil Velikov2014-01-183-1/+14
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50: typecast the result of ffs() to unsignedEmil Velikov2014-01-181-1/+1
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50: assert before trying to out-of-bounds access constbufEmil Velikov2014-01-183-0/+4
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50: access only the available amount of constbufEmil Velikov2014-01-181-1/+1
| | | | | | | | | | The textures array is defined as a number of NV50_MAX_PIPE_CONSTBUFS per shader stage. Currently the nv50 driver handles only 3 shader stages, thus we wreck chaos when accessing array-out-of-bounds. Cc: 9.1 9.2 10.0 <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50: access only the available amount of texturesEmil Velikov2014-01-181-1/+1
| | | | | | | | | | | | The textures array is defined as a number of PIPE_MAX_SAMPLERS per shader stage. Currently nv50 driver handles only 3 shader stages, thus we wreck chaos when accessing array-out-of-bounds. Fixes a segfault in piglit/bin/arb_texture_buffer_object-data-sync -fbo -auto Cc: 9.1 9.2 10.0 <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* s/Tungsten Graphics/VMware/José Fonseca2014-01-17126-289/+289
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the old copyright name is creating unnecessary confusion, hence this change. This was the sed script I used: $ cat tg2vmw.sed # Run as: # # git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed # # Rename copyrights s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g /Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./ s/TUNGSTEN GRAPHICS/VMWARE/g # Rename emails s/[email protected]/[email protected]/ s/[email protected]/[email protected]/g s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/ s/jrfonseca\[email protected]/[email protected]/g s/keithw\[email protected]/[email protected]/g s/[email protected]/[email protected]/g s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/ s/[email protected]/[email protected]/ # Remove dead links s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g # C string src/gallium/state_trackers/vega/api_misc.c s/"Tungsten Graphics, Inc"/"VMware, Inc"/ Reviewed-by: Brian Paul <[email protected]>
* trace: Re-license trace.xsl under MIT license.José Fonseca2014-01-171-14/+22
| | | | | | | I was the sole author, as Tungsten Graphics employee, which was since then acquired by VMware Inc. Reviewed-by: Brian Paul <[email protected]>
* svga: fix crash when clearing null color bufferBrian Paul2014-01-171-3/+7
| | | | | | | | | | Fixes regression since 9baa45f78b8ca7d66280e36009b6a685055d7cd6 but some of the piglit fbo-drawbuffers-none tests still don't pass. v2: use the right pointer type for 'h' Reviewed-by: José Fonseca <[email protected]>
* llvmpipe: handle NULL color buffer pointersBrian Paul2014-01-175-94/+156
| | | | | | | | | Fixes regression from 9baa45f78b8ca7d66280e36009b6a685055d7cd6 v2: incorporate a few small changes suggested by Roland. Reviewed-by: José Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* softpipe: handle NULL color buffer pointersBrian Paul2014-01-171-93/+96
| | | | | | Fixes regression from 9baa45f78b8ca7d66280e36009b6a685055d7cd6 Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: fix large point rasterization with point_quad_rasterizationRoland Scheidegger2014-01-171-12/+19
| | | | | | | | | | The whole round-pointsize-to-int stuff must only be done with GL legacy rules (no point_quad_rasterization) or all the wrong edges are lit up. This was previously in a private branch (d3d pointsprite test complains loudly otherwise) and got lost in a merge. However, it should certainly apply to GL point sprite rasterization as well. Reviewed-by: Jose Fonseca <[email protected]>
* gallium: add bits for clipping points as tris (d3d-style)Roland Scheidegger2014-01-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | OpenGL does whole-point clipping, that is a large point is either fully clipped or fully unclipped (the latter means it may extend beyond the viewport as long as the center is inside the viewport). d3d9 (d3d10 has no large points) however requires points to be clipped after they are expanded to a rectangle. (Note some IHVs are known to ignore GL rules at least with some hw/drivers.) Hence add a rasterizer bit indicating which way points should be clipped (some drivers probably will always ignore this), and add the draw interaction this requires. Drivers wanting to support this and using draw must support large points on their own as draw doesn't implement vp clipping on the expanded points (it potentially could but the complexity doesn't seem warranted), and the driver needs to do viewport scissoring on such points. Conflicts: src/gallium/drivers/llvmpipe/lp_context.c src/gallium/drivers/llvmpipe/lp_state_derived.c Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: do constant buffer bounds checking in shadersZack Rusin2014-01-164-4/+20
| | | | | | | | | | | | | | | | | | | | It's possible to bind a smaller buffer as a constant buffer, than what the shader actually uses/requires. This could cause nasty crashes. This patch adds the architecture to pass the maximum allowable constant buffer index to the jit to let it make sure that the constant buffer indices are always within bounds. The behavior follows the d3d10 spec, which says the overflow should always return all zeros, and overflow is only defined as access beyond the size of the currently bound buffer. Accesses beyond the declared shader constant register size are not considered an overflow and expected to return garbage but consistent garbage (we follow the behavior which some wlk tests expect which is to return the actual values from the bound buffer). Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* nv50, nvc0: initialize ctx->sample_mask to ~0Ilia Mirkin2014-01-162-0/+4
| | | | | | | | | | Commit 95bf222603b (cso_context: Fix cso_context::sample_mask initial value.) fixed the cso sample mask to be initialized to ~0. The cso code is also careful not to needlessly call set_sample_mask, so we ended up with the ctx->sample_mask never being set. This broke a number of EXT_framebuffer_multisample piglit tests. Signed-off-by: Ilia Mirkin <[email protected]>
* radeon: Move gfx/dma cs cleanup to r600_common_context_cleanupAaron Watry2014-01-162-7/+7
| | | | | | | | | | | The radeonsi code was not cleaning up either of these items leading to leaked memory. v2: Move cleanup to r600_common_context_cleanup instead of duplicating the logic for SI CC: "10.0" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ilo: handle NULL renderbuffers correctlyChia-I Wu2014-01-146-27/+45
| | | | Renderbuffers may be NULL since 9baa45f78b8ca7d66280e36009b6a685055d7cd6.
* ilo: disable HiZ for misaligned levelsChia-I Wu2014-01-144-82/+215
| | | | | | | | | | | | | | We need to disable HiZ for non-8x4 aligned levels, except for level 0, layer 0. For the very first layer we can adjust Width and Height fields of 3DSTATE_DEPTH_BUFFER to make it aligned. Specifically, add ILO_TEXTURE_HIZ and set the flag only for properly aligned levels. ilo_texture_can_enable_hiz() is updated to check for the flag. In tex_layout_validate(), align the depth bo to 8x4 so that we can adjust Width/Height of 3DSTATE_DEPTH_BUFFER without introducing out-of-bound access. Finally in rectlist blitter, add the ability to adjust 3DSTATE_DEPTH_BUFFER.
* ilo: use a helper to determine if HiZ is enabledChia-I Wu2014-01-145-8/+19
| | | | | Add ilo_texture_can_enable_hiz and replace all checks for tex->hiz.bo by calls to ilo_texture_can_enable_hiz().
* ilo: decide on hiz first in texture allocationChia-I Wu2014-01-141-64/+64
| | | | | | | | | Add tex_layout_init_hiz() before tex_layout_init_format() to decide whether HiZ should be enabled. On GEN6, because of layer offsetting, HiZ is enabled only when the texture is non-mipmapped and non-array. PIPE_USAGE_STAGING is also taken as a hint to disable HiZ.
* ilo: emit gen7_wa_pipe_control_wm_max_threads_stall on HaswellChia-I Wu2014-01-141-7/+9
| | | | | | | Rename the workaround, as it is for 3DSTATE_PS instead of 3DSTATE_WM, and emit it on Haswell too. This does not fix any app, but an assertion failure.
* ilo: use HALIGN_4 on GEN7 for depth buffersChia-I Wu2014-01-141-11/+1
| | | | The comment was no longer true since 6642381e7513926b847d6bc10bf590e1c0c54859.
* ilo: OOM for HiZ is fatal on GEN6Chia-I Wu2014-01-141-2/+7
| | | | On GEN6, HiZ and Separate Stencil Buffer must be enabled at the same time.
* ilo: fix a HiZ bo leakageChia-I Wu2014-01-141-0/+3
| | | | Dereference the HiZ bo when the texture is destroyed.
* ilo: simplify ilo_texture_set_slice_flags()Chia-I Wu2014-01-141-5/+3
| | | | | Call ilo_texture_get_slice() for the last slice so that we can get rid of the duplicated assert().
* radeonsi: Rename the commonly occurring rscreen variable.Andreas Hartmetz2014-01-143-86/+86
| | | | | | The "r" stands for R600. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Rename the commonly occurring rctx/r600 variables.Andreas Hartmetz2014-01-1418-757/+757
| | | | | | The "r" stands for R600. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Rename r600_trace_emit->si_trace_emit.Andreas Hartmetz2014-01-142-2/+2
| | | | | | I had previously considered that unsafe. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Rename R600->SI in some remaining defines.Andreas Hartmetz2014-01-148-22/+22
| | | | | | I had previously considered that unsafe. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Rename radeonsi->si remaining identifiers in si_uvd.c.Andreas Hartmetz2014-01-141-2/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Rename r600->si remaining identifiers in si_state_draw.c.Andreas Hartmetz2014-01-141-2/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Rename r600->si remaining identifiers in si_resource.c.Andreas Hartmetz2014-01-141-6/+6
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Rename r600->si remaining identifiers in si_query.c.Andreas Hartmetz2014-01-141-18/+18
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Rename r600->si remaining identifiers in si_pipe.c.Andreas Hartmetz2014-01-141-36/+36
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Rename r600->si remaining identifier in si_hw_context.c.Andreas Hartmetz2014-01-141-1/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Rename radeonsi->si remaining identifiers in si_compute.c.Andreas Hartmetz2014-01-141-8/+8
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Rename r600->si remaining identifiers in si_blit.c.Andreas Hartmetz2014-01-141-110/+110
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Rename r600->si for functions in si_pipe.h.Andreas Hartmetz2014-01-1412-57/+57
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Rename r600->si for functions in si.h.Andreas Hartmetz2014-01-144-46/+46
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Rename r600->si for functions in si_resource.h.Andreas Hartmetz2014-01-149-17/+17
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Rename r600->si for structs in si_resource.h.Andreas Hartmetz2014-01-143-7/+7
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Rename r600->si for structs in si.h.Andreas Hartmetz2014-01-143-24/+24
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Rename r600->si for structs in si_pipe.h.Andreas Hartmetz2014-01-1420-195/+195
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Apply si_* file naming scheme.Andreas Hartmetz2014-01-1424-107/+79
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g: fix glClearBuffer by handling PIPE_CLEAR_COLORi flags correctlyMarek Olšák2014-01-131-38/+31
| | | | also restructure the code
* r600g: handle NULL colorbuffers correctly on R600-R700Marek Olšák2014-01-131-65/+55
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* r600g: handle NULL colorbuffers correctly on EvergreenMarek Olšák2014-01-132-28/+54
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* radeonsi: handle NULL colorbuffers correctlyMarek Olšák2014-01-131-9/+11
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* llvmpipe: Honour pipe_rasterizer::point_quad_rasterization.José Fonseca2014-01-091-10/+57
| | | | | | | | | | | | Commit eda21d2a3010d9fc5a68b55a843c5e44b2abf8dd fixed the rasterization of points for Direct3D but ended up breaking the rasterization of OpenGL non-sprite points, in particular conform's pntrast.c test. The only way to get both working is to properly honour pipe_rasterizer::point_quad_rasterization, and follow the weird OpenGL rule when it is false. Reviewed-by: Roland Scheidegger <[email protected]>
* mesa: Work around internal compiler errorThomas Sondergaard2014-01-081-2/+2
| | | | | | | | | This small rearrangement avoids MSVC 2013 ICE. Also, this should be a better memory access order. Cc: "10.0" <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* freedreno: add basic query supportRob Clark2014-01-088-1/+275
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add for now some simple/basic query support (ie. things not actually requiring the GPU). Might change around a bit when I actually add GPU queries, but for now this enables some useful performance info in the GALLIUM_HUD. For example: GALLIUM_HUD=fps+batches+batches-sysmem+batches-gmem+restores,draw-calls The driver specific specific queries are: + draw-calls + batches - number of batches per second, sum of batches-sysmem plus batches-gmem + batches-gmem - render a set of tiles in GMEM, for each tile (optionally) system mem -> gmem (restore), plus N draws, plus gmem -> system mem (resolve) per second + batches-sysmem - N draws to system memory (GMEM bypass) per second + restores - number of GMEM batches that required restore per second Ideally for GMEM rendering, you want batches-gmem to equal fps. If the app is doing something that triggers multiple passes (ie. requires extra round trip gmem <-> system memory) then the # of batches per second will go up relative to fps. Signed-off-by: Rob Clark <[email protected]>
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