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* vc4: Enable LIT lowering in TGSI instead of our own code.Eric Anholt2014-10-081-35/+1
| | | | This brings us the -128/128 clamping on the w component.
* vc4: Fix scalar math opcodes to replicate their result from the X channel.Eric Anholt2014-10-081-4/+16
| | | | | Thanks to robclark for pointing out that I was probably failing to do this when I reported a "bug" in his lowering code.
* ilo: fix rectlist on GEN7+Chia-I Wu2014-10-091-0/+3
| | | | | | It was broken by 343b014b57ecc5431477e090100e6a26edbda540. Signed-off-by: Chia-I Wu <[email protected]>
* vc4: Add support for two-sided color.Eric Anholt2014-10-082-18/+51
| | | | | | | | | | It's fairly easy, thanks to Rob Clark's lowering code. Fixes two-sided-lighting and 4 vertex-program-two-side testcases, while regressing 8 testcases that involve enabling two-sided color while only initializing one of the two colors in the VS. If you're enabling two sided color, it's of course expected that you really do set up both colors, so this is still an improvement (and when we set up a linker for TGSI, we'll hopefully fix those 8 fails).
* vc4: Enable POW lowering in TGSI instead of our own code.Eric Anholt2014-10-081-11/+1
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* vc4: Enable DP lowering in TGSI instead of our own code.Eric Anholt2014-10-081-41/+3
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* vc4: Start using tgsi_lowering for opcodes we haven't supported before.Eric Anholt2014-10-081-1/+15
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* vc4: Set unused raddr fields to QPU_R_NOP.Eric Anholt2014-10-081-16/+27
| | | | | | | The simulator assertion fails if you have a write to a reg and then a read (for example, in the NOP side of an instruction), even if the read isn't used for anything. By setting unused raddrs to NOP, we avoid the problem (since only the phsyical registers are tracked).
* vc4: Abstract out the field-merging logic for instructions.Eric Anholt2014-10-081-11/+17
| | | | I'm going to be doing the same logic for some more fields next.
* r600: Use DMA transfers in r600_copy_global_bufferNiels Ole Salscheider2014-10-072-17/+43
| | | | | | v2: Do not demote items that are already in the pool Signed-off-by: Niels Ole Salscheider <[email protected]>
* radeonsi: Use dummy pixel shader if compilation of the real shader failedMichel Dänzer2014-10-073-7/+22
| | | | | | | Instead of crashing. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79155#c5 Reviewed-by: Marek Olšák <[email protected]>
* ilo: let shaders determine surface countsChia-I Wu2014-10-069-202/+267
| | | | | | | | When a shader needs N surfaces, we should upload N surfaces and not depend on how many are bound. This commit is larger than it should be because we did not export how many surfaces a surface uses before. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: let shaders determine sampler countsChia-I Wu2014-10-0413-87/+98
| | | | | | | When a shader needs N samplers, we should upload N samplers and not depend on how many are bound. Signed-off-by: Chia-I Wu <[email protected]>
* tgsi: change tgsi_shader_info::properties to a one-dimensional arrayMarek Olšák2014-10-048-15/+15
| | | | | | Reviewed-by: Roland Scheidegger <[email protected]> v2: fix svga too
* radeonsi: set number of userdata SGPRs of GS copy shader to 4Marek Olšák2014-10-043-10/+23
| | | | | | | It only needs the constant buffer with clip planes and read-write resources for the GS->VS ring and streamout. That's 2 pointers. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: pass the GS shader directly to si_generate_gs_copy_shaderMarek Olšák2014-10-041-3/+3
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: set LLVMByValAttribute for all descriptor arraysMarek Olšák2014-10-041-10/+7
| | | | | | I hope this is correct. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: make the vertex shader key smallerMarek Olšák2014-10-041-1/+2
| | | | | | We only support 16 vertex attribs, not 32. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: don't flush shader caches when building PM4 shader statesMarek Olšák2014-10-041-8/+0
| | | | | | | | | This is a wrong place to flush caches to say the least. I don't think we need to flush the instruction caches if we don't patch shaders with DMA. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove interp_at_sample from the key, use TGSI_INTERPOLATE_LOC_SAMPLEMarek Olšák2014-10-043-5/+2
| | | | | | | | | st/mesa has the same flag in its shader key, we don't need to do it in the driver anymore. Instead, use TGSI_INTERPOLATE_LOC_SAMPLE, which is what st/mesa sets. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: move geometry shader properties from si_shader to si_shader_selectorMarek Olšák2014-10-044-29/+38
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: always compile shaders on demandMarek Olšák2014-10-041-13/+3
| | | | | | | The first compiled shader is sometimes useless, because the key doesn't match the key for the draw call where it's used. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove unused variable si_shader::gs_input_primMarek Olšák2014-10-042-3/+0
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* tgsi: remove some not so useful variables from tgsi_shader_infoMarek Olšák2014-10-044-9/+14
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* radeonsi: get fs_write_all from tgsi_shader_info directlyMarek Olšák2014-10-043-16/+3
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* tgsi: simplify shader properties in tgsi_shader_infoMarek Olšák2014-10-044-68/+27
| | | | Use an array of properties indexed by TGSI_PROPERTY_* definitions.
* radeonsi: get tgsi_shader_info only once before compilationMarek Olšák2014-10-043-21/+16
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix CS tracing and remove excessive CS dumpingMarek Olšák2014-10-043-35/+25
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* gk110/ir: add dnz flag emission for fmul/fmadIlia Mirkin2014-10-031-0/+4
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.2 10.3" <[email protected]>
* gm107/ir: add dnz emission for fmulIlia Mirkin2014-10-031-1/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.3" <[email protected]>
* freedreno: query fixesRob Clark2014-10-033-8/+13
| | | | | | | Fixes a few issues, including a potential empty-IB (which triggers gpu hangs in piglit occlusion_query_meta_no_fragments) Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: handle VS only outputting BCOLORRob Clark2014-10-031-2/+10
| | | | | | | Possibly we should map the front color to black (zeroes). But not sure there is a way to do that without generating a shader variant. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix lockups with lame FRAG shadersRob Clark2014-10-034-6/+17
| | | | | | | | | | | | | | | | | | | | | | | | Shaders like: FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: TEX TEMP[0], IN[0].xyyy, SAMP[0], 2D 1: MOV OUT[0], IMM[0].xyxx 2: END cause unhappyness. They have an IN[], but once this is compiled the useless TEX instruction goes away. Leaving a varying that is never fetched, which makes the hw unhappy. In the process fix a signed vs unsigned compare. If the vertex shader has max_reg=-1, MAX2() vs an unsigned would not give the desired result. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add TXF supportIlia Mirkin2014-10-021-1/+39
| | | | | | | Still failing a bunch of the fairly picky texelFetch tests, but the 1D(Array) ones are full passes. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: add TXD support and expose ARB_shader_texture_lodIlia Mirkin2014-10-023-9/+56
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: add texture offset supportIlia Mirkin2014-10-021-4/+45
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: shadow comes before arrayIlia Mirkin2014-10-021-2/+2
| | | | | | | Experimentally, this makes *ArrayShadow tex-miplevel-selection tests pass. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: make TXQ return integers, not floatsIlia Mirkin2014-10-021-1/+1
| | | | | | We're still doing something wrong for array textures. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: add UMAD supportIlia Mirkin2014-10-021-4/+15
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: add ISSG supportIlia Mirkin2014-10-021-0/+39
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: add MOD supportIlia Mirkin2014-10-021-8/+12
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: add UMOD support, based on UDIVIlia Mirkin2014-10-021-6/+31
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: add IDIV/UDIV supportIlia Mirkin2014-10-021-3/+197
| | | | | | Logic shamelessly copied from nv50 lowering pass. Signed-off-by: Ilia Mirkin <[email protected]>
* radeonsi: Clear sampler view flags when binding a bufferMichel Dänzer2014-10-031-0/+5
| | | | | | | | | Fixes assertion failure while running the Unreal Engine 4 Elemental demo: .../si_blit.c:322:si_decompress_color_textures: Assertion `tex->cmask.size || tex->fmask.size' failed. Cc: "10.2 10.3" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* vc4: Add support for framebuffer sRGB encoding.Eric Anholt2014-10-021-2/+31
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* vc4: Add support for sampling from sRGB.Eric Anholt2014-10-022-9/+51
| | | | | | | | This isn't perfect -- the filtering is happening on the srgb values, and we're decoding afterwards, which is not what you want. I think that's the cause of some additional texwrap(GL_CLAMP, LINEAR) failures, though many other texwrap tests on srgb start to pass since unfiltered values come out correct.
* freedreno/ir3: avoid fan-in sources referring to same instructionIlia Mirkin2014-10-021-2/+10
| | | | | | | | | | Since the RA has to be done s.t. each one gets its own (adjacent) register, it would complicate matters if instructions were allowed to be repeated. This enables copy-propagation use in situations where previously that might have happened. Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: emit all immediates in one shotRob Clark2014-10-021-8/+16
| | | | | | | Makes the command stream a bit tighter when there are lots of immediates. Signed-off-by: Rob Clark <[email protected]>
* freedreno: instanced drawing/compute not yet supportedIlia Mirkin2014-10-021-3/+3
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: handle large shader program sizesRob Clark2014-10-021-11/+63
| | | | | | | Above a certain limit use CACHE mode instead of BUFFER mode. This should solve gpu hangs with large shader programs. Signed-off-by: Rob Clark <[email protected]>
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