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* winsys/amdgpu: add support for allocating GDS and OA resourcesMarek Olšák2018-11-281-1/+3
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: allow si_cp_dma_clear_buffer to clear GDS from any IBMarek Olšák2018-11-284-31/+33
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* winsys/amdgpu,radeon: pass vm_alignment to buffer_from_handleMarek Olšák2018-11-284-3/+10
| | | | Acked-by: Christian König <[email protected]>
* radeonsi: fix is_oneway_access_only for bindless imagesMarek Olšák2018-11-281-6/+23
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* radeonsi/nir: parse more information about bindless usageMarek Olšák2018-11-281-4/+32
| | | | fill more tgsi_shader_info fields.
* radeonsi: small cleanup for memory opcodesMarek Olšák2018-11-281-9/+4
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* radeonsi: fix is_oneway_access_only for image storesMarek Olšák2018-11-281-12/+37
| | | | We need to look at the Dst for image stores.
* radeonsi: use structured buffer intrinsics for image viewsMarek Olšák2018-11-282-10/+42
| | | | to stop using the workaround in si_make_buffer_descriptor.
* radeonsi: clean up primitive binning enablementMarek Olšák2018-11-281-11/+16
| | | | | | no change in behavior. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* virgl: fix undefined shift to use unsigned.Dave Airlie2018-11-291-1/+1
| | | | | | Ported from virglrenderer. Signed-off-by: Dave Airlie <[email protected]>
* r600: make suballocator 256-bytes alignDave Airlie2018-11-291-1/+1
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108311 Cc: <[email protected]>
* winsys/amdgpu: explicitly declare whether buffer_map is permanent or notNicolai Hähnle2018-11-2814-28/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a new driver-private transfer flag RADEON_TRANSFER_TEMPORARY that specifies whether the caller will use buffer_unmap or not. The default behavior is set to permanent maps, because that's what drivers do for Gallium buffer maps. This should eliminate the need for hacks in libdrm. Assertions are added to catch when the buffer_unmap calls don't match the (temporary) buffer_map calls. I did my best to update r600 for consistency (r300 needs no changes because it never calls buffer_unmap), even though the radeon winsys ignores the new flag. As an added bonus, this should actually improve the performance of the normal fast path, because we no longer call into libdrm at all after the first map, and there's one less atomic in the winsys itself (there are now no atomics left in the UNSYNCHRONIZED fast path). Cc: Leo Liu <[email protected]> v2: - remove comment about visible VRAM (Marek) - don't rely on amdgpu_bo_cpu_map doing an atomic write Reviewed-by: Marek Olšák <[email protected]>
* virgl: Don't try handling server fences when they are not supportedGert Wollny2018-11-281-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | vtest doesn't implement the according API and would segfault: Program received signal SIGSEGV, Segmentation fault. #0 0x0000000000000000 in ?? () #1 in virgl_fence_server_sync at src/gallium/drivers/virgl/virgl_context.c:1049 #2 in st_server_wait_sync at src/mesa/state_tracker/st_cb_syncobj.c:155 so just don't do the call when the function pointers are not set. Fixes dEQP: dEQP-GLES3.functional.fence_sync.wait_sync_smalldraw dEQP-GLES3.functional.fence_sync.wait_sync_largedraw Fixes: d1a1c21e7621b5177febf191fcd3d3b8ef69dc96 virgl: native fence fd support Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Robert Foss <[email protected]>
* v3d: Add renderonly support.Eric Anholt2018-11-274-4/+68
| | | | | | I've been using this with the kmsro series to test v3d on VKMS without my old KMS hack in the v3d kernel driver. KMSRO still needs some cleanup, but v3d RO support seems reasonable.
* freedreno: implements get_sample_positionHyunjun Ko2018-11-271-0/+45
| | | | | | | | | | Since 1285f71d3e landed, it needs to provide apps with proper sample position for MSAA. Currently no way to query this to hw, these are taken from blob driver. Fixes: dEQP-GLES31.functional.texture.multisample.samples_#.sample_position Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: also set FSSUPERTHREADENABLERob Clark2018-11-271-0/+1
| | | | | | | | | | We set equiv bit in SP_FS_CTRL_REG0. Somehow the hw doesn't hang with this mismatched config, but does run slower. It is faster with either neither bit set, or both bits set, but both is the fastest of the three configurations. Worth a bit over 10% gain in glmark2. Spotted-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno: use MSM_BO_SCANOUT with scanout buffersJonathan Marek2018-11-271-1/+3
| | | | Signed-off-by: Jonathan Marek <[email protected]>
* freedreno: use GENERIC instead of TEXCOORD for blit programJonathan Marek2018-11-271-1/+1
| | | | | | | blip_fp uses GENERIC as input, so blit_vp should match for linking Signed-off-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno: a2xx texture updateJonathan Marek2018-11-279-20/+212
| | | | | | | | | | | Adds all missing texture related logic. For everything to work it also needs changes to ir2/fd2_program, which are part of the ir2 update patch. Note: it needs rnndb update Signed-off-by: Jonathan Marek <[email protected]> [remove stray patch] Signed-off-by: Rob Clark <[email protected]>
* freedreno/a2xx: Compute depth base in gmem correctlyJonathan Marek2018-11-271-5/+7
| | | | | | | | Note: it needs rnndb update Signed-off-by: Marek Vasut <[email protected]> Signed-off-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a2xx: set VIZ_QUERY_ID on a20xJonathan Marek2018-11-271-0/+5
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno: add missing a20x idsJonathan Marek2018-11-271-0/+2
| | | | | | | | 200: 256KiB GMEM A200 (imx53) 201: 128KiB GMEM A200 (imx51) Signed-off-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a2xx: fix POINT_MINMAX_MAX overflowJonathan Marek2018-11-271-1/+1
| | | | | | | As it stands, it overflows to zero. Signed-off-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno: a2xx: fd2_draw updateJonathan Marek2018-11-276-20/+114
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-11-277-39/+287
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: set guardband clipRob Clark2018-11-274-7/+57
| | | | | | | | | On older gens, the CLIP_ADJ bitfields were actually 3.6 fixed point. Which might make more sense. Although this formula comes up with values pretty close to what blob does for various viewport sizes (for at least a5xx and a6xx), and seems to work. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: disable LRZ for z32Rob Clark2018-11-271-1/+13
| | | | | | | | | f6131d4ec7a had the side effect of enabling LRZ w/ 32b depth buffers. But there are some bugs with this, which aren't fully understood yet, so for now just skip LRZ w/ z32.. Fixes: f6131d4ec7a freedreno/a6xx: Clear z32 and separate stencil with blitter Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: Clear gmem buffers at flush timeKristian H. Kristensen2018-11-274-178/+180
| | | | | | | | | We generate an IB to clear the gmem at flush time and jump to it before rendering each tile. This lets us get rid of the command stream patching for gmem offsets. Signed-off-by: Kristian H. Kristensen <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: Move resolve blits to an IBKristian H. Kristensen2018-11-273-8/+29
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: Move restore blits to IBKristian H. Kristensen2018-11-273-19/+49
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno: move ir3 to common locationRob Clark2018-11-2740-13732/+37
| | | | | | | | | | | | | | | | Move (most of) the ir3 compiler to src/freedreno/ir3 so that it can be re-used by some future vulkan driver. The parts that are gallium specific have been refactored out and remain in the gallium driver. Getting the move done now so that it can happen before further refactoring to support a6xx specific instructions. NOTE also removes ir3_cmdline compiler tool from autotools build since that was easier than fixing it and I normally use meson build. Waiting patiently for the day that we can remove *everything* from the autotools build. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove u_inlines usageRob Clark2018-11-271-10/+10
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split up ir3_shaderRob Clark2018-11-2714-667/+766
| | | | | | | Split the parts that are gallium specific into ir3_gallium so the rest can move to a common location outside of gallium. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove pipe_stream_output_info dependencyRob Clark2018-11-278-17/+68
| | | | | | | | A bit annoying to have to copy into our own struct. But this is something the compiler really needs to know, at least on earlier generations where streamout is implemented in shader. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: some header file cleanupRob Clark2018-11-2711-26/+24
| | | | | | Clean up some of the low-hanging-fruit usages of freedreno_util.h Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use env_var_as_unsigned()Rob Clark2018-11-272-14/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move disasm and optmsgs debug flagsRob Clark2018-11-279-22/+25
| | | | | | | Move them to IR3_SHADER_DEBUG so we can remove ir3's dependency on fd_mesa_debug. Signed-off-by: Rob Clark <[email protected]>
* freedreno: FD_SHADER_DEBUG -> IR3_SHADER_DEBUGRob Clark2018-11-274-33/+34
| | | | | | Only used by ir3, so move it into ir3 to be more self contained. Signed-off-by: Rob Clark <[email protected]>
* freedreno: remove shader_stage_name()Rob Clark2018-11-273-21/+3
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: shader_t -> gl_shader_stageRob Clark2018-11-2722-143/+121
| | | | | | | | | Just massive search/replace for the most part. Step towards removing ir3 dependency on disasm.h which is shared by a2xx. One step closer to being able to move ir3 out of gallium. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: standalone compiler updatesRob Clark2018-11-271-6/+27
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: move drm to common locationRob Clark2018-11-2720-3717/+12
| | | | | | | | So that we can re-use at least parts of it for vulkan driver, and so that we can move ir3 to a common location (which uses fd_bo to allocate storage for shaders) Signed-off-by: Rob Clark <[email protected]>
* freedreno/drm: remove dependency on gallium driverRob Clark2018-11-271-2/+11
| | | | | | | | Prep work to move drm to a common location. Slightly hacky, but the softpin debug flag is only temporary. Signed-off-by: Rob Clark <[email protected]>
* nv50/ir: remove dnz flag when converting MAD to ADD due to optimizationsIlia Mirkin2018-11-241-0/+3
| | | | | | | | | | dnz flag only applies for multiplications (e.g. to make 0 * Infinity becomes 0 instead of NaN). Once we optimize a MAD into an ADD, the dnz flag no longer makes sense, and upsets the GM107 emitter (since it looks at the ftz and dnz flags together). Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Karol Herbst <[email protected]>
* virgl: add assert and missing function parameterRobert Foss2018-11-211-1/+4
| | | | | | | | | | Verify the pipe_fd_type to be of PIPE_FD_TYPE_NATIVE_SYNC. Fixes: d1a1c21e7621b5177feb "virgl: native fence fd support" Suggested-by: Eric Engestrom <[email protected]> Signed-off-by: Robert Foss <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* r600: clean up the GS ring buffers when the context is destroyedGert Wollny2018-11-211-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes two memory leaks reported by ASAN: Direct leak of 248 byte(s) in 1 object(s) allocated from: in malloc (/usr/lib64/gcc/x86_64-pc-linux-gnu/7.3.0/libasan.so+0xdb880) in r600_alloc_buffer_struct ../../samba/mesa/src/gallium/drivers/r600/r600_buffer_common.c:578 in r600_buffer_create ../../samba/mesa/src/gallium/drivers/r600/r600_buffer_common.c:600 in r600_resource_create_common ../../samba/mesa/src/gallium/drivers/r600/r600_pipe_common.c:1265 in r600_resource_create ../../samba/mesa/src/gallium/drivers/r600/r600_pipe.c:725 in pipe_buffer_create ../../samba/mesa/src/gallium/auxiliary/util/u_inlines.h:291 in update_gs_block_state ../../samba/mesa/src/gallium/drivers/r600/r600_state_common.c:1482 Direct leak of 248 byte(s) in 1 object(s) allocated from: in malloc (/usr/lib64/gcc/x86_64-pc-linux-gnu/7.3.0/libasan.so+0xdb880) in r600_alloc_buffer_struct ../../samba/mesa/src/gallium/drivers/r600/r600_buffer_common.c:578 in r600_buffer_create ../../samba/mesa/src/gallium/drivers/r600/r600_buffer_common.c:600 in r600_resource_create_common ../../samba/mesa/src/gallium/drivers/r600/r600_pipe_common.c:1265 in r600_resource_create ../../samba/mesa/src/gallium/drivers/r600/r600_pipe.c:722 in pipe_buffer_create ../../samba/mesa/src/gallium/auxiliary/util/u_inlines.h:291 in update_gs_block_state ../../samba/mesa/src/gallium/drivers/r600/r600_state_common.c:1489 Signed-off-by: Gert Wollny <[email protected]> Fixes: 1371d65a7fbd695d3516861fe733685569d890d0 r600g: initial support for geometry shaders on evergreen (v2) Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi: go back to using bottom-of-pipe for beginning of TIME_ELAPSEDMarek Olšák2018-11-201-11/+4
| | | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102597 Cc: 18.3 <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: don't send data after write-confirm with BOTTOM_OF_PIPE_TSMarek Olšák2018-11-203-9/+5
| | | | | | | There are no writes. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* meson: Add tests to suitesDylan Baker2018-11-202-2/+4
| | | | | | | | | | | | | | | | Meson test has a concepts of suites, which allow tests to be grouped together. This allows for a subtest of tests to be run only (say only the tests for nir). A test can be added to more than one suite, but for the most part I've only added a test to a single suite, though I've added a compiler group that includes nir, glsl, and glcpp tests. To use this you'll need to invoke meson test directly, instead of ninja test (which always runs all targets). it can be invoked as: `meson test -C builddir --suite $suitename` (meson test has addition options that are pretty useful). Tested-By: Gert Wollny <[email protected]> Acked-by: Eric Engestrom <[email protected]>
* nir: Make nir_lower_clip_vs optionally work with variables.Kenneth Graunke2018-11-192-2/+3
| | | | | | | | | | | | The way nir_lower_clip_vs() works with store_output intrinsics makes a ton of assumptions about the driver_location field. In i965 and iris, I'd rather do this lowering early and work with variables. v3d may want to switch to that as well, and ir3 could too, but I'm not sure exactly what would need updating. For now, handle both methods. Reviewed-by: Eric Anholt <[email protected]>
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