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* radeon/uvd: add Define Restart Interval to MJPEG bitstream reconstructionLeo Liu2017-09-021-0/+11
* radeon/uvd: fix MJPEG quantization table indexLeo Liu2017-09-021-1/+1
* freedreno: skip batch-cache for compute shadersRob Clark2017-09-021-7/+1
* swr: Report format max_samples=1 to maintain support for "fake" msaa.Cherniak, Bruce2017-09-011-11/+11
* radeonsi: move si_vm_fault_occured() to AMD common codeSamuel Pitoiset2017-09-011-102/+4
* nvc0/ir: propagate immediates to CALL input MOVsTobias Klausmann2017-08-311-2/+19
* nvc0: write 0 to pipeline_statistics.cs_invocationsKarol Herbst2017-08-311-0/+1
* radeonsi: set a per-buffer flag that disables inter-process sharing (v4)Marek Olšák2017-08-312-4/+23
* svga: include sample count in surface_size() computationBrian Paul2017-08-301-1/+1
* radeonsi: update dirty_level_mask before dispatchingSamuel Pitoiset2017-08-302-0/+6
* llvmpipe: initialize llvmpipe->dirty with LP_NEW_SCISSORBrian Paul2017-08-291-0/+6
* ac/debug: Support multiple trace ids for nested IBs.Bas Nieuwenhuizen2017-08-291-9/+10
* radeonsi: stop leaking nirTimothy Arceri2017-08-291-0/+1
* radeonsi: rewrite late alloc VS limit computationMarek Olšák2017-08-281-12/+25
* gallium/radeon: set EVENT_WRITE_EOP.INT_SEL = wait for write confirmationMarek Olšák2017-08-281-3/+9
* gallium/u_threaded: rename IGNORE_VALID_RANGE -> NO_INFER_UNSYNCHRONIZEDMarek Olšák2017-08-281-1/+1
* radeonsi: correct maximum wave count per SIMDMarek Olšák2017-08-281-1/+12
* i915g: Remove a few unused variablesEduardo Lima Mitev2017-08-281-16/+0
* Revert "radeonsi: get the raster config from AMDGPU on SI"Marek Olšák2017-08-271-17/+0
* etnaviv: use correct param for etna_compatible_rs_format(..)Christian Gmeiner2017-08-261-1/+1
* a2xx: fix DST_ALPHA blending for non-alpha formatsIlia Mirkin2017-08-253-5/+21
* a2xx: set constant blend colorIlia Mirkin2017-08-251-0/+9
* radeonsi: set IF_THRESHOLD to 4Timothy Arceri2017-08-251-1/+1
* glsl: pass shader source keys to the disk cacheTimothy Arceri2017-08-251-1/+1
* radeonsi: get the raster config from AMDGPU on SIMarek Olšák2017-08-241-0/+17
* radeonsi: clean up setting GRBM_GFX_INDEXMarek Olšák2017-08-241-19/+22
* radeonsi: move PA_SC_RASTER_CONFIG emission into a separate functionMarek Olšák2017-08-241-70/+73
* nv50/ir: properly set sType for TXF ops to U32Ilia Mirkin2017-08-241-0/+3
* swr: limit pipe_draw_info->restart_index usageTim Rowley2017-08-231-1/+4
* radeonsi: fix wrong assertion in si_init_bindless_descriptors()Samuel Pitoiset2017-08-231-1/+1
* radeon/video: Return false explicitly for HEVC if not the caseLeo Liu2017-08-231-0/+1
* gallium/radeon: fix saving multi-part command streamsNicolai Hähnle2017-08-231-1/+1
* radeonsi: update comment describing indices into sctx->descriptorsNicolai Hähnle2017-08-231-6/+5
* radeonsi: do not assert when reserving bindless slot 0Samuel Pitoiset2017-08-231-1/+4
* radeonsi: rename some bindless-related helper functionsSamuel Pitoiset2017-08-231-21/+21
* radeonsi: minor cleanups in si_make_{texture,image}_handle_resident()Samuel Pitoiset2017-08-231-12/+12
* radeon/vcn: enable P016 mode supportLeo Liu2017-08-221-7/+11
* radeon/vcn: correct target buffer pitch calculationLeo Liu2017-08-221-1/+1
* gallium: remove TGSI opcode SCSMarek Olšák2017-08-2210-309/+4
* gallium: remove TGSI opcode BREAKCMarek Olšák2017-08-223-45/+3
* gallium: remove TGSI opcode XPDMarek Olšák2017-08-2212-317/+3
* gallium: remove TGSI opcode DPHMarek Olšák2017-08-2210-139/+3
* gallium: remove TGSI opcode DP2AMarek Olšák2017-08-225-57/+3
* gallium: remove TGSI_OPCODE_CALLNZMarek Olšák2017-08-222-4/+3
* gallium: remove TGSI FENCE opcodesMarek Olšák2017-08-222-19/+9
* gallium: remove TGSI opcodes PUSHA, POPA, SAD, TXQ_LZMarek Olšák2017-08-223-23/+16
* radeonsi: emit VGT_REUSE_OFF in the right placeMarek Olšák2017-08-222-8/+9
* radeonsi: add support for TGSI opcodes DCEIL, DFLR, DROUND, DSSG, DTRUNCMarek Olšák2017-08-222-1/+15
* radeonsi: use a faster version of PK2HMarek Olšák2017-08-221-21/+8
* radeonsi: don't decompress Z/S if there is no HTILEMarek Olšák2017-08-221-12/+15
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