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* freedreno: introduce fd_batchRob Clark2016-07-3020-177/+252
| | | | | | | | | | | | | | | | | | | Introduce the batch object, to track a batch/submit's worth of ringbuffers and other bookkeeping. In this first step, just move the ringbuffers into batch, since that is mostly uninteresting churn. For now there is just a single batch at a time. Note that one outcome of this change is that rb's are allocated/freed on each use. But the expectation is that the bo pool in libdrm_freedreno will save us the GEM bo alloc/free which was the initial reason to implement a rb pool in gallium. The purpose of the batch is to eventually facilitate out-of-order rendering, with batches associated to framebuffer state, and tracking the dependencies on other batches. Signed-off-by: Rob Clark <[email protected]>
* freedreno: limit non-user constant buffers to a4xxRob Clark2016-07-291-1/+1
| | | | | | | Seems to mostly work on a3xx. Except when it doesn't and kills gpu quite badly. Signed-off-by: Rob Clark <[email protected]>
* vc4: automake: remove vc4_drm.h from the sources listsEmil Velikov2016-07-281-1/+0
| | | | | | | | | The file was removed with earlier commit breaking 'make dist'. Drop it from Makefile.sources since it's no longer around. Fixes: 16985eb308e ("vc4: Switch to using the libdrm-provided vc4_drm.h.") Signed-off-by: Emil Velikov <[email protected]>
* ddebug: use pclose to close a popen()'d FILENicolai Hähnle2016-07-281-1/+1
| | | | | | Found by Coverity. Reviewed-by: Marek Olšák <[email protected]>
* nvc0: enable ARB_tessellation_shader on GM107+Samuel Pitoiset2016-07-271-3/+0
| | | | | | | This exposes OpenGL 4.1 on Maxwell (tested on GM107 and GM206). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gm107/ir: add a legalize SSA pass for PFETCHSamuel Pitoiset2016-07-274-2/+43
| | | | | | | PFETCH, actually ISBERD on GM107+ ISA only accepts a GPR for src0. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: fix up TCP header on GM107+Samuel Pitoiset2016-07-271-0/+9
| | | | | | | | | | The number of outputs patch (limited to 255) has moved in the TCP header, but blob seems to also set the old position. Also, the high 8-bits are now located inbetween the min/max parallel output read address at position 20. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* radeon/llvm: Use alloca instructions for larger arrays [revert a revert]Marek Olšák2016-07-262-25/+149
| | | | | | This reverts commit f84e9d749fbb6da73a60fb70e6725db773c9b8f8. Bioshock Infinite no longer hangs.
* r600g: add support for B5G6R5 PBO uploads via texture buffers (v2)Marek Olšák2016-07-261-0/+6
| | | | | | v2: set endian swap to 16 untested
* radeonsi: pre-generate shader logs for ddebugMarek Olšák2016-07-264-6/+34
| | | | | | | | This cuts down the overhead of si_dump_shader when ddebug is capturing shader logs, which is done for every draw call unconditionally (that's quite a lot of work for a draw call). Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add empty lines after shader statsMarek Olšák2016-07-261-1/+1
| | | | | | to separate individual shaders dumped consecutively. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move the shader key dumping to si_shader_dumpMarek Olšák2016-07-263-5/+9
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ddebug: implement pipelined hang detection modeMarek Olšák2016-07-264-4/+567
| | | | | | | | | | | | | | | | | | | | | | For good performance while being able to generate decent hang reports. The report doesn't contain the parsed IB and the buffer list, but it isolates the draw call and dumps shaders while not having to flush the context. This is for GPU hangs that are harder to reproduce and require interactive playing for minutes or even hours. dd_pipe.h explains some implementation details. Initializing, copying (recording) and clearing states is most of the code. The performance should be at least 50% of the normal performance depending on the circumstances. (i.e. 50% is expected to be the worst case scenario, not the best case) The majority of time is spent in dump_debug_state(PIPE_DUMP_CURRENT_SHADERS) and that's after all the optimizations in later patches. There is no obvious way to optimize that further. Reviewed-by: Nicolai Hähnle <[email protected]>
* ddebug: don't save pointers to call parametersMarek Olšák2016-07-262-6/+6
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ddebug: move dd_call into dd_pipe.hMarek Olšák2016-07-262-66/+66
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ddebug: separate draw call dumping logicMarek Olšák2016-07-261-21/+26
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ddebug: move all states into a separate structureMarek Olšák2016-07-263-129/+140
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ddebug: write contents of dmesg into hang reportsMarek Olšák2016-07-261-4/+25
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ddebug: implement create_batch_queryMarek Olšák2016-07-261-0/+27
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ddebug: don't use abort()Marek Olšák2016-07-261-1/+1
| | | | | | We don't want a core dump. Reviewed-by: Nicolai Hähnle <[email protected]>
* ddebug: make dd_get_file_stream accept the screen onlyMarek Olšák2016-07-261-7/+8
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ddebug: clean up ddebug_screen_createMarek Olšák2016-07-261-16/+23
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: rework flags for pipe_context::dump_debug_stateMarek Olšák2016-07-262-15/+29
| | | | | | | | The pipelined hang detection mode will not want to dump everything. (and it's also time consuming) It will only dump shaders after a draw call and then dump the status registers separately if a hang is detected. Reviewed-by: Nicolai Hähnle <[email protected]>
* vc4: add hash table look-up for exported dmabufsRob Herring2016-07-264-3/+56
| | | | | | | | | | | | | It is necessary to reuse existing BOs when dmabufs are imported. There are 2 cases that need to be handled. dmabufs can be created/exported and imported by the same process and can be imported multiple times. Copying other drivers, add a hash table to track exported BOs so the BOs get reused. v2: Whitespace fixup (by anholt) Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* vc4: Disable early Z with computed depth.Eric Anholt2016-07-263-2/+11
| | | | | We don't tell the hardware whether we're computing depth, so we need to manage early Z state manually. Fixes piglit early-z.
* nvc0: use nvc0_m2mf_push_linear() to reduce code duplicationSamuel Pitoiset2016-07-261-13/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: use nve4_p2mf_push_linear() to reduce code duplicationSamuel Pitoiset2016-07-261-36/+9
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: upload sample locations on GM20xSamuel Pitoiset2016-07-243-5/+31
| | | | | | | | This fixes a bunch of multisample piglit tests on GM206, like bin/arb_texture_multisample-texelfetch 2 -auto -fbo Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* freedreno/a4xx: time-elapsed query should be active for clearsRob Clark2016-07-241-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* nvc0/ir: fix up an assertion in emitUADD()Samuel Pitoiset2016-07-241-4/+3
| | | | | | | | It's illegal to have neg modifiers on both sources for OP_ADD, and it's illegal to have OP_SUB with just src0 neg. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: fix wrong indentation in nvc0_validate_fb()Samuel Pitoiset2016-07-231-141/+141
| | | | | | Trivial. Signed-off-by: Samuel Pitoiset <[email protected]>
* freedreno/a4xx: timestamp queriesRob Clark2016-07-233-1/+34
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: hw timestamp supportRob Clark2016-07-232-2/+15
| | | | | | If the kernel supports it, use hw counter for timestamps. Signed-off-by: Rob Clark <[email protected]>
* freedreno: prep work for timestamp queriesRob Clark2016-07-233-6/+10
| | | | | | | | | We need "NULL" state to be a valid bit in the bitmask, because timestamp queries are not restricted to draw/etc stages (ie. the only commands to submit may just be to read the timestamp). And just because there are no draws, isn't a reason to skip the flush and return zero. Signed-off-by: Rob Clark <[email protected]>
* radeonsi: ensure sample locations are set for line and polygon smoothingNicolai Hähnle2016-07-231-2/+1
| | | | | | | Since commit d938b8c, the sample locations are no longer set unconditionally, so we need to set the atom to dirty on all chips, not just Polaris. Cc: 12.0 <[email protected]>
* radeonsi: fix Polaris MSAA regressionNicolai Hähnle2016-07-232-15/+20
| | | | | | | | | | | | | The regression was introduced by commit d938b8c. The problem here is that in order to use the small primitive filter, we need to explicitly set the sample locations to 0. But the DB doesn't properly process the change of sample locations without a flush, and so we can end up with incorrect Z values. Instead of doing a flush, just disable the small primitive filter when MSAA is force-disabled. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96908 Cc: 12.0 <[email protected]>
* freedreno/ir3: Add missing braces in initializer[email protected]2016-07-231-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a2xx: silence missing case 'SHADER_COMPUTE' warning (v2)[email protected]2016-07-231-0/+2
| | | | | | | v2: no need for break after an unreachable (Matt Turner) Signed-off-by: Francesco Ansanelli <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* radeonsi: implement buffer_subdata without indirect callsMarek Olšák2016-07-235-5/+41
| | | | | | There is less noise in CPU profile data now. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/util: don't modify usage in pipe_buffer_writeMarek Olšák2016-07-231-0/+5
| | | | | | All drivers were already doing it except virgl. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: split transfer_inline_write into buffer and texture callbacksMarek Olšák2016-07-2334-132/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | to reduce the call indirections with u_resource_vtbl. The worst call tree you could get was: - u_transfer_inline_write_vtbl - u_default_transfer_inline_write - u_transfer_map_vtbl - driver_transfer_map - u_transfer_unmap_vtbl - driver_transfer_unmap That's 6 indirect calls. Some drivers only had 5. The goal is to have 1 indirect call for drivers that care. The resource type can be determined statically at most call sites. The new interface is: pipe_context::buffer_subdata(ctx, resource, usage, offset, size, data) pipe_context::texture_subdata(ctx, resource, level, usage, box, data, stride, layer_stride) v2: fix whitespace, correct ilo's behavior Reviewed-by: Nicolai Hähnle <[email protected]> Acked-by: Roland Scheidegger <[email protected]>
* nv50/ir: allow to swap sources for OP_SUBSamuel Pitoiset2016-07-221-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the load-propagation pass to swap the sources in presence of immediate values. Maxwell (GM107): total instructions in shared programs :1928187 -> 1927634 (-0.03%) total gprs used in shared programs :330741 -> 330154 (-0.18%) total local used in shared programs :28032 -> 28032 (0.00%) local gpr inst bytes helped 0 271 425 425 hurt 0 0 194 194 Fermi (GF114): total instructions in shared programs :2334474 -> 2333829 (-0.03%) total gprs used in shared programs :380934 -> 380215 (-0.19%) total local used in shared programs :33304 -> 33264 (-0.12%) local gpr inst bytes helped 5 314 521 521 hurt 0 4 195 195 No regressions on GM107 and GF114 with full piglit. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium/radeon: make deferred flushes asynchronousMarek Olšák2016-07-221-0/+2
| | | | Reviewed-by: Edward O'Callaghan <[email protected]>
* nvc0/mme: fix offsets used for indirect drawsSamuel Pitoiset2016-07-222-8/+8
| | | | | | | | | | This fixes a regression introduced in 1da704a94c57aa0b0cf8faaa3236fe47dfb8f88c because the offset has moved from 0x180 to 0x1a0, and the macros have to be re-compiled. Fixes: 1da704a ("nvc0: increase the tex handles area size in the driver") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: fix offsets of MP perf counters input parametersSamuel Pitoiset2016-07-221-15/+15
| | | | | | | | | | | | | This fixes a regression introduced in 1da704a94c57aa0b0cf8faaa3236fe47dfb8f88c because the offset has moved from 0x600 to 0x620, and the kernels used for reading MP perf counters have to be re-assembled. This also fixes amd_performance_monitor_measure piglit. Fixes: 1da704a ("nvc0: increase the tex handles area size in the driver") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* vc4: Return V3D version details in the GL renderer info.Eric Anholt2016-07-202-1/+12
| | | | This is as close as we get to a name for the 3D blocks.
* vc4: Check the V3D version reported by the kernel.Eric Anholt2016-07-202-0/+62
| | | | | | We don't want to bring up an old userspace driver on a kernel for newer hardware. We'll also want to look at the other ident fields in the future.
* vc4: Detect and report kernel support for branching.Eric Anholt2016-07-201-2/+12
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* vc4: Switch to using the libdrm-provided vc4_drm.h.Eric Anholt2016-07-202-280/+2
| | | | | The required version is set to .69 for the getparam ioctl that will be used in the next commit.
* swr: [rasterizer core] introduce simd16intrin.hTim Rowley2016-07-204-6/+751
| | | | | | | | | Refactoring to leave existing simd_* intrinsics in "simdintrin.h" unchanged, adding corresponding simd16_* intrinsics in "simd16intrin.h" on the side, with emulation, that we can use piecemeal, rather than the all-or-nothing approach to bring up avx512. Signed-off-by: Tim Rowley <[email protected]>
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