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* radeon/vce: add firmware support for ver 53 and upBoyuan Zhang2018-05-111-2/+2
| | | | | | | All vce firmwares with major version greater than or equal to 53 are supported Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* etnaviv: remove pipe_fence_handle::ctxRob Clark2018-05-111-2/+0
| | | | | | | | | A fence can outlive the ctx it was created from (see glmark2).. etnaviv doesn't actually need fence->ctx so lets remove it before someone makes the mistake of assuming it is a valid pointer. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* swr/rast: Thread locked tiles improvementGeorge Kyriazis2018-05-117-24/+152
| | | | | | | - Change tilemgr TILE_ID encoding to use Morton-order (Z-order). - Change locked tiles set to bitset. Makes clear, set, get much faster. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add Builder::GetVectorType()George Kyriazis2018-05-112-0/+45
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Prepend the console output with a newlineGeorge Kyriazis2018-05-111-1/+1
| | | | | | It can get jumbled with output from other threads. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add ConcatLists()George Kyriazis2018-05-111-0/+6
| | | | | | for concatenating lists Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add constant initializer for uint64_tGeorge Kyriazis2018-05-112-0/+6
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Use binner topology to assemble backend attributesGeorge Kyriazis2018-05-111-1/+1
| | | | | | | | Previously was using the draw topology, which may change if GS or Tess are active. Only affected attributes marked with constant interpolation, which limited the impact. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Change formattingGeorge Kyriazis2018-05-111-1/+6
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* ac/gpu_info: add has_read_registers_queryMarek Olšák2018-05-101-3/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add has_2d_tilingMarek Olšák2018-05-101-5/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add has_sparse_vm_mappingsMarek Olšák2018-05-101-11/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add has_unaligned_shader_loadsMarek Olšák2018-05-101-5/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: expose ARB_query_buffer_object on ancient kernels tooMarek Olšák2018-05-101-3/+1
| | | | | | It doesn't use indirect dispatches. Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add has_indirect_compute_dispatchMarek Olšák2018-05-101-13/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add kernel_flushes_tc_l2_after_ibMarek Olšák2018-05-101-2/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add has_format_bc1_through_bc7Marek Olšák2018-05-101-6/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add has_eqaa_surface_allocatorMarek Olšák2018-05-101-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clean up the reset status query implementationMarek Olšák2018-05-102-23/+18
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add has_bo_metadataMarek Olšák2018-05-101-2/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add si_TA_CS_BC_BASE_ADDR_allowedMarek Olšák2018-05-101-3/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add htile_cmask_support_1d_tilingMarek Olšák2018-05-102-9/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/gpu_info: add kernel_flushes_hdp_before_ibMarek Olšák2018-05-101-4/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add an environment variable that forces EQAA for MSAA allocationsMarek Olšák2018-05-104-5/+59
| | | | | | This is for testing and experiments. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set up EQAA image descriptors properlyMarek Olšák2018-05-101-16/+80
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add EQAA SC,DB,CB register programmingMarek Olšák2018-05-102-8/+71
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: support creating EQAA color texturesMarek Olšák2018-05-103-17/+33
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: add EQAA supportMarek Olšák2018-05-103-6/+7
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use better sample locations for 8x EQAAMarek Olšák2018-05-101-21/+11
| | | | | | Verified with the piglit MSAA accuracy test. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: improve quality of 16 sample locationsMarek Olšák2018-05-101-2/+2
| | | | | | | This results in better 16x and 8x quality when using these locations. Verified with the piglit MSAA accuracy test. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use better sample locations for 4x MSAAMarek Olšák2018-05-101-11/+10
| | | | | | | | | | | Discovered by luck. Verified with the piglit MSAA accuracy test. It also shows that the worst case EQAA 16s4f results in very good 4x MSAA in the worst case. Nine might not like these positions, but they are prettier to the eye and GL doesn't care. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: reorder sample locations as required by EQAAMarek Olšák2018-05-102-59/+98
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: simplify si_get_sample_positionMarek Olšák2018-05-101-29/+20
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: simplify arrays of sample locationsMarek Olšák2018-05-101-65/+40
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set DB_EQAA the same as VulkanMarek Olšák2018-05-101-8/+8
| | | | | | These never change, but they only affect EQAA, which isn't implemented. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove CM_ prefixesMarek Olšák2018-05-101-4/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't update clear color registers if they don't changeMarek Olšák2018-05-101-11/+21
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove r600_fmask_infoMarek Olšák2018-05-106-87/+46
| | | | | | radeon_surf contains almost everything. Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: unify common legacy and gfx9 fmask fieldsMarek Olšák2018-05-101-8/+8
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface/gfx6: compute FMASK together with the color surfaceMarek Olšák2018-05-101-41/+7
| | | | | | instead of invoking FMASK computation separately. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: work around a GPU hang due to broken indirect indexing in LLVMMarek Olšák2018-05-101-0/+9
| | | | | | Fixes: 6d19120da85 "radeonsi/gfx9: workaround for INTERP with indirect indexing" Cc: 18.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* virgl: Add support for passing GL_ANY_SAMPLES_PASSED_CONSERVATIVEGert Wollny2018-05-101-1/+2
| | | | | | | | This is needed for fixing CTS: dEQP-GLES3.functional.occlusion_query.conservative* Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Gert Wollny <[email protected]>
* r600: fix constant buffer bounds.Dave Airlie2018-05-102-2/+2
| | | | | | | | | | | | | | | | | | | | If you have an indirect access to a constant buffer on r600/eg use a vertex fetch in the shader. However apps have expected behaviour on those out of bounds accessess (even if illegal). If the constants were being uploaded as part of a larger upload buffer, we'd set the range of allowed access to a lot larger than required so apps would get values back from other parts of the upload buffer instead of the expected out of bounds access. This fixes rendering bugs in Trine and Witcher 1, thanks to iive for nagging me effectively until I figured it out :-) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91808 Cc: <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* eg/compute: Drop reference to kernel_param bo in destructorJan Vesely2018-05-081-0/+1
| | | | | | CC: <[email protected]> Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600: Cleanup constant buffers on context destructionJan Vesely2018-05-081-1/+5
| | | | | | CC: <[email protected]> Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* eg/compute: Drop reference on code_bo in destructor.Jan Vesely2018-05-071-3/+1
| | | | | Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* swr/rast: Fix include for createInstructionCombiningPass with llvm-7.0.Vinson Lee2018-05-051-0/+1
| | | | | | | | | | | | | | | Fix build error after llvm-7.0.0svn r330669 ("InstCombine: Fix layering by not including Scalar.h in InstCombine"). CXX rasterizer/jitter/libmesaswr_la-blend_jit.lo rasterizer/jitter/blend_jit.cpp:816:20: error: use of undeclared identifier 'createInstructionCombiningPass'; did you mean 'createInstructionSimplifierPass'? passes.add(createInstructionCombiningPass()); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ createInstructionSimplifierPass Suggested-by: George Kyriazis <[email protected]> Signed-off-by: Vinson Lee <[email protected]> Reviewed-By: George Kyriazis <[email protected]>
* nv50/ir: fix printing of pixldRhys Perry2018-05-031-1/+1
| | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* swr/rast: Fix WriteBitcodeToFile usage with llvm-7.0.Vinson Lee2018-05-031-0/+4
| | | | | | | | | | | | | | Fix build error after llvm-7.0svn r325155 ("Pass a reference to a module to the bitcode writer."). CXX rasterizer/jitter/libmesaswr_la-JitManager.lo rasterizer/jitter/JitManager.cpp:548:30: error: reference to type 'const llvm::Module' could not bind to an lvalue of type 'const llvm::Module *' llvm::WriteBitcodeToFile(M, bitcodeStream); ^ Suggested-by: George Kyriazis <[email protected]> Signed-off-by: Vinson Lee <[email protected]> Reviewed-By: George Kyriazis <[email protected]>
* nv50: Extract needed value bits without shifting them before calling bitcountVlad Golovkin2018-05-021-1/+1
| | | | | | | This can save one instruction since bitcount doesn't care about specific bits' positions. Reviewed-by: Karol Herbst <[email protected]>
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