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* radeonsi/nir: implement ac_shader_abi::load_sampler_descNicolai Hähnle2017-07-313-20/+49
* ac/nir,radeonsi: add ac_shader_abi::chip_classNicolai Hähnle2017-07-311-0/+2
* radeonsi/nir: emit FS outputsNicolai Hähnle2017-07-311-10/+14
* radeonsi/nir: load FS inputsNicolai Hähnle2017-07-313-11/+52
* radeonsi/nir: load VS inputsNicolai Hähnle2017-07-313-2/+40
* ac/nir,radeonsi: add ac_shader_abi::load_uboNicolai Hähnle2017-07-311-0/+14
* ac,radeonsi: add ac_shader_abi::emit_outputs for hardware VS shadersNicolai Hähnle2017-07-312-11/+33
* radeonsi: pass si_shader_context to get_primitive_idNicolai Hähnle2017-07-311-6/+5
* radeonsi: translate NIR to LLVMNicolai Hähnle2017-07-313-3/+21
* radeonsi: dump NIR instead of TGSI when appropriateNicolai Hähnle2017-07-311-1/+5
* radeonsi: bypass the shader cache for NIR shadersNicolai Hähnle2017-07-311-2/+3
* radeonsi: scan NIR shaders to obtain required infoNicolai Hähnle2017-07-315-6/+335
* radeonsi: add si_shader_selector::nirNicolai Hähnle2017-07-311-0/+3
* radeonsi: implement pipe_screen::get_compiler_options for NIRNicolai Hähnle2017-07-311-0/+33
* radeonsi: add nir include pathsNicolai Hähnle2017-07-311-0/+1
* ac,radeonsi: move some VS input descriptions to ac_shader_abiNicolai Hähnle2017-07-312-31/+37
* radeonsi: store shader function arguments in a structureNicolai Hähnle2017-07-311-300/+322
* gallium/targets: link against NIR when building radeonsiNicolai Hähnle2017-07-311-0/+3
* st/glsl_to_nir: move nir_lower_io to driversNicolai Hähnle2017-07-312-0/+9
* st/mesa: get rid of st_glsl_typesNicolai Hähnle2017-07-314-10/+26
* gallium: add PIPE_CAP_NIR_SAMPLERS_AS_DEREFNicolai Hähnle2017-07-3115-0/+15
* radeonsi: expose MRT-draw-calls to HUDMarek Olšák2017-07-314-0/+11
* radeonsi: update dirty_level_mask only when flushing or unbinding framebufferMarek Olšák2017-07-285-43/+59
* radeonsi: rely on CLEAR_STATE for clearing UCP and blend color registersMarek Olšák2017-07-283-2/+12
* radeonsi: rely on CLEAR_STATE for resetting the framebuffer and sample maskMarek Olšák2017-07-281-3/+10
* radeonsi: use CLEAR_STATE to initialize some registersMarek Olšák2017-07-281-54/+4
* virgl: drop precise modifier.Dave Airlie2017-07-281-0/+10
* radeonsi: bail out instead of crashing if the main shader part failed to compileNicolai Hähnle2017-07-271-0/+3
* radeonsi: update a comment for merged shadersNicolai Hähnle2017-07-271-1/+5
* radeonsi/gfx9: dump previous stage LLVM IR for merged shadersNicolai Hähnle2017-07-271-0/+7
* radeonsi: make sure TCS main output VGPRs don't alias inputsNicolai Hähnle2017-07-271-5/+13
* radeonsi/gfx9: always wrap GS and TCS in an if-block (v2)Nicolai Hähnle2017-07-272-33/+79
* radeonsi/gfx9: fix vertex idx in ES with multiple waves per threadgroupNicolai Hähnle2017-07-271-1/+6
* swr: fix transform feedback logicGeorge Kyriazis2017-07-274-8/+71
* swr/rast: non-regex knob fallback code for gcc < 4.9Tim Rowley2017-07-271-0/+21
* virgl: encode index buffer offset.Dave Airlie2017-07-271-1/+1
* radeonsi: decrease the number of compiler threadsMarek Olšák2017-07-262-3/+8
* gallium/radeon: make S_FIXED function signed and move it to shared codeMarek Olšák2017-07-263-9/+5
* radeonsi/gfx9: reduce max threads per block to 1024 on gfx9+Nicolai Hähnle2017-07-261-15/+24
* radeonsi: fix detection of DRAW_INDIRECT_MULTI on SINicolai Hähnle2017-07-261-2/+2
* broadcom/vc4: Use the RA callback to improve register selection's choices.Eric Anholt2017-07-251-1/+52
* broadcom/vc4: Scissor blits performed using the rendering engine.Eric Anholt2017-07-251-0/+9
* broadcom/vc4: Prefer blit via rendering to the software fallback.Eric Anholt2017-07-251-6/+8
* broadcom/vc4: Switch the Viewport Center fields to a fixed-point representation.Eric Anholt2017-07-251-2/+2
* broadcom/vc4: Use the XML decoder for CL dumping.Eric Anholt2017-07-253-443/+32
* svga: implement MSAA alpha_to_one featureBrian Paul2017-07-255-1/+57
* svga: rework the FS white fragments codeBrian Paul2017-07-252-33/+21
* r600: Add support for B5G5R5A1.Michal Srb2017-07-251-0/+6
* radeon/vcn: move message buffer to vram for nowLeo Liu2017-07-251-1/+2
* trace: Correct transfer box size calculation.Jose Fonseca2017-07-251-9/+8