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* freedreno/ir3: add missing put_dstRob Clark2014-09-121-0/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: catch incorrect usage of tmp-dstRob Clark2014-09-121-0/+15
| | | | | | | Each get_dst() should have a matching put_dst(). Add a bit of checking to catch mistakes. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use unsigned comparison for UIFIlia Mirkin2014-09-121-4/+4
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: negate result of USLT/etcIlia Mirkin2014-09-121-8/+15
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add UARL supportIlia Mirkin2014-09-121-2/+4
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: INEG operates on src0, not src1Ilia Mirkin2014-09-121-1/+3
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix FSLT/etc handling to return 0/-1 instead of 0/1.0Ilia Mirkin2014-09-121-4/+8
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: alpha render-target shenanigansRob Clark2014-09-124-2/+34
| | | | | | | | | We need the .w component to end up in .x, since the hw appears to fetch gl_FragColor starting with the .x coordinate regardless of MRT format. As long as we are doing this, we might as well throw out the remaining unneeded components. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: format fixesRob Clark2014-09-123-5/+20
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-09-124-4/+6
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: handle rendering to layer != 0Rob Clark2014-09-121-2/+12
| | | | Signed-off-by: Rob Clark <[email protected]>
* r300g: set register classes before interferencesConnor Abbott2014-09-121-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 567e2769b81863b6dffdac3826a6b729ce6ea37c ("ra: make the p, q test more efficient") I unknowingly introduced a new requirement to the register allocator API: the user must set the register class of all nodes before setting up their interferences, because ra_add_conflict_list() now uses the classes of the two interfering nodes. i965 already did this, but r300g was setting up register classes interleaved with setting up the interference graph. This led to us calculating the wrong q total, and in certain cases e78a01d5e6f77e075fe667a0f0ccb10d89c0dd58 (" ra: optimistically color only one node at a time") made it so that this bug caused a segfault. In particular, the error occurred if the q total was decremented to 1 below 0 for the last node to be pushed onto the stack. Since q_total is an unsigned integer, it overflowed to 0xffffffff, which is what lowest_q_total happens to be initialzed to. This means that we would fail the "new_q_total < lowest_q_total" check on line 476 of register_allocate.c, and so the node would never be pushed onto the stack, which led to segfaults in ra_select() when we failed to ever give it a register. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82828 Cc: "10.3" <[email protected]> Signed-off-by: Connor Abbott <[email protected]> Tested-by: Pavel Ondračka <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* ilo: fix builder size checks for BLT buffer clear/copyChia-I Wu2014-09-121-4/+8
| | | | | | | | | In buf_clear_region() and buf_copy_region(), max_cmd_size was set to 0. If either of the functions is called and there is not enough space in the builder, the next ilo_cp_flush() will fail silently in a release build. Replace magic numbers by size defines in tex_clear_region()/tex_copy_region() for consistency and readability.
* ilo: reduce BLT function parametersChia-I Wu2014-09-122-142/+171
| | | | | Intruduce gen6_blt_bo and gen6_blt_xy_bo to describe BOs. In the extreme case of gen6_XY_SRC_COPY_BLT(), the number of parameters goes down from 18 to 8.
* ilo: clean up BLT functionsChia-I Wu2014-09-122-104/+91
| | | | Follow the changes for MI functions, but for BLT this time.
* ilo: clean up MI functionsChia-I Wu2014-09-123-40/+45
| | | | | With ilo_builder in place, some conventions we had to build commands are no longer needed.
* ilo: move BLT functions to ilo_builder_blt.hChia-I Wu2014-09-123-257/+296
| | | | Follow the changes for MI functions, but for BLT this time.
* ilo: move MI functions to ilo_builder_mi.hChia-I Wu2014-09-128-168/+192
| | | | | Have a centralized place for MI functions, and remove the duplicated gen6_MI_LOAD_REGISTER_IMM().
* ilo: add ILO_DEV_ASSERT()Chia-I Wu2014-09-125-113/+118
| | | | It replaces ILO_GPE_VALID_GEN().
* ilo: use an accessor for dev->genChia-I Wu2014-09-1224-171/+198
| | | | | It should enable us to do specialized builds by making the accessor return a constant.
* ilo: add GEN_EXTRACT() and GEN_SHIFT32()Chia-I Wu2014-09-124-133/+142
| | | | They replace READ() and SET_FIELD() that we have been using.
* ilo: remove ILO_GEN_GET_MAJOR()Chia-I Wu2014-09-121-1/+0
| | | | The last user has gone away.
* ilo: careful with empty fb state in ilo_gpe_set_fb()Chia-I Wu2014-09-122-1/+6
| | | | We cannot pass 0 as the width or height to ilo_gpe_init_view_surface_null().
* nv50,nvc0: enable ARB_texture_viewIlia Mirkin2014-09-124-6/+6
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: add a texture target to sampler view and a CAP to use itIlia Mirkin2014-09-1213-0/+13
| | | | | | | | | | This allows a sampler view to have a different texture target than the underlying resource. This will be used to implement the type casting between 2d arrays and cube maps as specified in ARB_texture_view. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nouveau: remove unneeded assertMaarten Lankhorst2014-09-111-1/+0
| | | | | | | | No idea why it was added, but the code runs fine even on videos where it triggers. Signed-off-by: Maarten Lankhorst <[email protected]> Cc: "10.2 10.3" <[email protected]>
* nouveau: rework reference frame handlingMaarten Lankhorst2014-09-113-4/+37
| | | | | | | | | | | | Fixes a regression from "nouveau/vdec: small fixes to h264 handling" New picking order for frames: 1. Vidbuf pointer matches. 2. Take the first kicked ref. 3. If that fails, take a ref that has a different last_used. Signed-off-by: Maarten Lankhorst <[email protected]> Cc: "10.2 10.3" <[email protected]>
* nouveau: fix MPEG4 hw decodingMaarten Lankhorst2014-09-111-3/+3
| | | | | | | Reorder some fields to make I-frame decoding work correctly. Signed-off-by: Maarten Lankhorst <[email protected]> Cc: "10.2 10.3" <[email protected]>
* nouveau: re-allocate bo's on overflowMaarten Lankhorst2014-09-114-11/+87
| | | | | | | | | The BSP bo might be too small to contain all of the bsp data, bump its size on overflow. Also bump inter_bo when this happens, it might be too small otherwise. Signed-off-by: Maarten Lankhorst <[email protected]> Cc: "10.2 10.3" <[email protected]>
* ilo: fix a compile error with -Werror=format-securityChia-I Wu2014-09-121-1/+1
| | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83777
* radeon/uvd: use PIPE_USAGE_STAGING for msg&fb buffersChristian König2014-09-111-1/+1
| | | | | | | | That better matches the actual userspace use case, the kernel will force it to VRAM if the hardware requires it. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeon/video: use the hw to initial clear the buffersChristian König2014-09-113-10/+8
| | | | | | | Less CPU overhead and avoids contention over CPU accessible memory on startup. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeon/video: use more of the common buffer code v2Christian König2014-09-116-67/+62
| | | | | | | | | In preparation to using buffers clears with the hw engine(s). v2: split out flipping to using hw buffer clears. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* ilo: add a new disassemblerChia-I Wu2014-09-113-4444/+1352
| | | | | | | | The old disassembler was modified from i965's. It is as much work as doing a new one to keep it up-to-date, which also requires copying more headers over. The outputs of this new disassembler should match i965's as closely as possible.
* ilo: update genhw headersChia-I Wu2014-09-1111-247/+203
| | | | | | | | Add some new registers and some tweaks. The changes that affect ilo are GEN6_REG_HS_INVOCATION_COUNT -> GEN7_REG_HS_INVOCATION_COUNT GEN6_REG_DS_INVOCATION_COUNT -> GEN7_REG_DS_INVOCATION_COUNT GEN6_COND_NORMAL -> GEN6_COND_NONE
* radeonsi: Simplify si_dma_copy_tile functionMichel Dänzer2014-09-111-62/+41
| | | | | | No functional change intended. Reviewed-by: Marek Olšák <[email protected]>
* vc4: Add support for shadow samplers.Eric Anholt2014-09-091-3/+58
| | | | | | | This doesn't quite make depth-tex-compare work, presumably because we're not hitting equality with itof(sample) * 1.0/0xffffff in the 0xffffff case. arb_fragment_program_shadow tests pass, though, as well as a bunch of other shadow-related stuff.
* vc4: Add support for texture swizzles.Eric Anholt2014-09-091-1/+8
| | | | Fixes depth-tex-modes.
* vc4: Move the texture format into a struct.Eric Anholt2014-09-091-3/+5
| | | | I'm going to be putting some bitfields into the struct as well.
* vc4: Add support for depth texturing.Eric Anholt2014-09-091-3/+13
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* vc4: Expose r4 to register allocation.Eric Anholt2014-09-094-23/+49
| | | | | | | | We potentially need to be careful that use of a value stored in r4 isn't copy-propagated (or something) across another r4 write. That doesn't appear to happen currently, and this makes the dataflow more obvious. It also opens up not unpacking the r4 value, which will be useful for depth textures.
* vc4: Drop pointless raddr conflict handling on SF.Eric Anholt2014-09-091-1/+0
| | | | SF doesn't have a src[1].
* vc4: The r4_count is supposed to be how many writes, not reads.Eric Anholt2014-09-091-1/+1
| | | | It's part of the key so that you can tell which r4 value is being read.
* r600g,radeonsi: Set RADEON_GEM_NO_CPU_ACCESS flag for tiled BOsMichel Dänzer2014-09-101-0/+1
| | | | | | | This lets the kernel know that such BOs can be pinned outside of the CPU accessible part of VRAM. Reviewed-by: Marek Olšák <[email protected]>
* freedreno/a3xx: enable hw primitive-restartRob Clark2014-09-094-9/+20
| | | | | | | | | | Since software primitive-restart emulation is going to be removed (and anyways, mostly seemed to be crash prone in combination with u_primconvert and oddball scenarios (like PIPE_PRIM_POLYGON with only a single vertex), might as well do it in hardware (which fortunately didn't turn out to be too hard to figure out). Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-09-094-13/+18
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix potential segfault in RARob Clark2014-09-091-2/+6
| | | | | | | | | | | | | | | | | | | | | | Triggered by shaders like: FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL OUT[0], COLOR DCL CONST[0] DCL TEMP[0..2], LOCAL 0: IF CONST[0].xxxx :0 1: MOV TEMP[0], TEMP[1] 2: ELSE :0 3: MOV TEMP[0], TEMP[2] 4: ENDIF 5: MOV OUT[0], TEMP[0] 6: END not really a sane shader, although driver segfaulting is probably not the appropriate response. Signed-off-by: Rob Clark <[email protected]>
* freedreno: don't overflow cmdstream buffer so muchRob Clark2014-09-091-0/+15
| | | | | | | | | | | | | | We currently aren't too clever about dealing with running out of cmdstream buffer space. Since we use a single buffer for both drawing and tiling commands, we need to ensure there is enough space at the tail of the cmdstream buffer to fit the tiling commands. Until we get more clever, the easy solution is a threshold to trigger flushing rendering even if the application does not trigger flush (swap, changing render target, etc). This way we at least don't crash for apps that do several thousand draw calls (like some piglit tests do). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add no-copy-propagate fallback stepRob Clark2014-09-093-11/+21
| | | | | | | | | | | Most of the things the new compiler still has trouble with basically amount to cp stage removing too many copies. But without the cp stage, the shaders the new compiler produces are still better (perf and correctness) than the old compiler. So a simple thing to do until I have more time to work on it is first trying falling back to new compiler without cp, before finally falling back to old compiler. Signed-off-by: Rob Clark <[email protected]>
* ilo: add ilo_builder.h to the sources listEmil Velikov2014-09-091-0/+1
| | | | Signed-off-by: Emil Velikov <[email protected]>
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