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* radeonsi: align scratch and ring buffer allocations for faster memory accessMarek Olšák2019-08-273-7/+11
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: consolidate determining VGPR_COMP_CNT for API VSMarek Olšák2019-08-271-44/+32
| | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: set PA_CL_VS_OUT_CNTL with CONTEXT_REG_RMW to fix edge flagsMarek Olšák2019-08-275-18/+59
| | | | | | | | | | We need two different values of the register, one for NGG and one for legacy, in order to fix edge flags for the legacy pipeline. Passing the ngg flag to emit_clip_regs would be too complicated, so CONTEXT_REG_RMW is used for partial register updates. Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: remove incorrect ngg/pos_writes_edgeflag variablesMarek Olšák2019-08-274-21/+14
| | | | | | It varies depending on si_shader_key::as_ngg. Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: add PKT3_CONTEXT_REG_RMWMarek Olšák2019-08-271-0/+30
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: add AMD_DEBUG=nonggMarek Olšák2019-08-272-1/+4
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: finish up Navi14, add PCI IDMarek Olšák2019-08-271-1/+2
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: always use the legacy pipeline for streamoutMarek Olšák2019-08-271-1/+1
| | | | | | The best way to prevent GDS hangs is not to use GDS. Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: don't initialize VGT_INSTANCE_STEP_RATE_0Marek Olšák2019-08-271-1/+2
| | | | | | Only gfx9 and older use it to get InstanceID in VGPR1. Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: fix InstanceID for legacy VS+GSMarek Olšák2019-08-271-4/+9
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: add as_ngg variant for VS as ES to select Wave32/64Marek Olšák2019-08-273-13/+12
| | | | | | Legacy GS only works with Wave64. Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: create the GS copy shader if using legacy streamoutMarek Olšák2019-08-271-1/+3
| | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: fix the PRIMITIVES_GENERATED query if using legacy streamoutMarek Olšák2019-08-273-4/+9
| | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: fix tessellation for the legacy pipelineMarek Olšák2019-08-271-0/+10
| | | | | | ported from PAL Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: move some global shader cache flags to per-binary flagsMarek Olšák2019-08-274-20/+23
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: fix the legacy pipeline by storing as_ngg in the shader cacheMarek Olšák2019-08-273-8/+9
| | | | | | It could load an NGG shader when we want a legacy shader and vice versa. Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* iris: Delete dead prototypeKenneth Graunke2019-08-271-2/+0
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* ac: add has_ls_vgpr_init_bug to ac_gpu_infoSamuel Pitoiset2019-08-274-5/+2
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: add has_msaa_sample_loc_bug to ac_gpu_infoSamuel Pitoiset2019-08-273-7/+2
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: add rbplus_allowed to ac_gpu_infoSamuel Pitoiset2019-08-274-19/+4
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: add has_gfx9_scissor_bug to ac_gpu_infoSamuel Pitoiset2019-08-274-8/+4
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: add cpdma_prefetch_writes_memory to ac_gpu_infoSamuel Pitoiset2019-08-273-4/+1
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: add has_out_of_order_rast to ac_gpu_infoSamuel Pitoiset2019-08-271-2/+1
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: add has_rbplus to ac_gpu_infoSamuel Pitoiset2019-08-273-4/+1
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: add has_dcc_constant_encode to ac_gpu_infoSamuel Pitoiset2019-08-274-6/+2
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: add has_distributed_tess to ac_gpu_infoSamuel Pitoiset2019-08-274-8/+3
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: add has_clear_state to ac_gpu_infoSamuel Pitoiset2019-08-274-9/+2
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* llvmpipe: flush on api memorybarrier.Dave Airlie2019-08-271-0/+9
| | | | | | Until we have somewhere we can do better, just hit it with a hammer. Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: bind vertex/geometry shader imagesDave Airlie2019-08-273-0/+126
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: add fragment shader image supportDave Airlie2019-08-2711-8/+334
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: introduce image jit type to fragment shader jit.Dave Airlie2019-08-272-2/+67
| | | | | | This adds the image type to the fragment shader jit context Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: move the fragment shader variant key to dynamic length.Dave Airlie2019-08-272-22/+46
| | | | | | | | | | This mirrors the vs/gs keys, and will be needed when adding images support. The const changes also mirror how the draw code work (as is needed when we add images) Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: handle early test property.Dave Airlie2019-08-271-2/+6
| | | | | | Also handle setting late for shaders that use stores Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: move first/last level jit texture members.Dave Airlie2019-08-272-10/+10
| | | | | | | This lets us create an image structure with the same basic types as the texture one. Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: refactor jit type creationDave Airlie2019-08-271-76/+87
| | | | | | | This just cleans the code up so the texture/sampler type creation can be reused. Reviewed-by: Roland Scheidegger <[email protected]>
* virgl: fix format conversion for recent gallium changes.Dave Airlie2019-08-266-16/+303
| | | | | | | | | | | | | | | | | | The virgl formats are fixed in time snapshots of the gallium ones, we just need to provide a translation table between them when we enter the hardware. This fixes a regression since Eric renumbered the gallium table. Fixes: c45c33a5a2 (gallium: Remove manual defining of PIPE_FORMAT enum values.) Bugzilla: https://bugs.freedesktop.org/111454 v1 by Dave Airlie <[email protected]> v2: virgl: Add a number of formats to the table that are used, e.g. for vertex attributes v3: cover some more missing formats from a piglit run Signed-off-by: Gert Wollny <[email protected]>
* lima/ppir: enable vectorize optimizationErico Nunes2019-08-251-0/+5
| | | | | | | | | | pp has vector units and some operations can be optimized when bundled together. Benchmarking this with piglit shaders shows that the instruction count can be greatly reduced on many examples with vectorize. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* lima/ppir: lower selects to scalarsErico Nunes2019-08-251-0/+5
| | | | | | | | | nir vec4 fcsel assumes that each component of the condition will be used to select the same component from the options, but pp can't implement that since it only has 1 component for the condition. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* lima: fix ppir spill stack allocationErico Nunes2019-08-254-9/+25
| | | | | | | | | | | | The previous spill stack was fixed and too small, and caused instability in programs requiring spilling for roughly more than one value. This patch adds a dynamic calculation of the buffer size based on stack utilization and switches it to a separate allocation at flush time that will fit the shader that requires the largest buffer. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* intel/fs: Drop the gl_program from fs_visitorJason Ekstrand2019-08-251-2/+2
| | | | | | | | | It's not used by anything anymore now that so much lowering has been moved into NIR. Sadly, we still need on in brw_compile_gs() for geometry shaders on Sandy Bridge. Short of a lot of pointless work, that one's probably not going away. Reviewed-by: Kenneth Graunke <[email protected]>
* lima: move format handling to unified placeQiang Yu2019-08-258-103/+190
| | | | | | | | | Create a unified table to handle pipe format to texture and render target format lookup. Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Qiang Yu <[email protected]>
* lima/ppir: print register index and components number for spilled registerVasily Khoruzhick2019-08-241-1/+3
| | | | | | | | | It can be useful for debugging purposes Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: add control flow supportVasily Khoruzhick2019-08-246-23/+168
| | | | | | | | | | This commit adds support for nir_jump_instr, if and loop nir_cf_nodes. Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: add better liveness analysisVasily Khoruzhick2019-08-245-74/+225
| | | | | | | | | | | Add better liveness analysis that was modelled after one in vc4. It uses live ranges and is aware of multiple blocks which is prerequisite for adding CF support Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: validate shader outputsVasily Khoruzhick2019-08-241-0/+13
| | | | | | | | Mali4x0 supports only gl_FragColor. gl_FragDepth is not supported. Check that we don't get anything but gl_FragColor in shader outputs. Reviewed-by: Qiang Yu <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: turn store_color into ALU nodeVasily Khoruzhick2019-08-234-61/+27
| | | | | | | | | | | | | We don't have a special OP to store color in PP, all we need to do is to store gl_FragColor into reg0, thus it's just a mov and therefore ALU node. Yet we still need to indicate that it's store_color op so regalloc ignores its destination. Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: create ppir block for each corresponding NIR blockVasily Khoruzhick2019-08-232-4/+49
| | | | | | | | | | | Create ppir block for each corresponding NIR block and populate its successors. It will be used later in liveness analysis and in CF support Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: add dummy opVasily Khoruzhick2019-08-233-5/+21
| | | | | | | | | | | | | | | | We can get following from NIR: (1) r1 = r2 (2) r2 = ssa1 Note that r2 is read before it's assigned, so there's no node for it in comp->var_nodes. We need to create a dummy node in this case which sole purpose is to hold ppir_dest with reg in it. Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: add write after read deps for registersVasily Khoruzhick2019-08-231-2/+25
| | | | | | | | | | | | | | | For cases like: (1) r1 = r2 (2) r2 = ssa1 We need to add (1) as dependency of (2), otherwise scheduler may reorder them. Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: fix ordering depsVasily Khoruzhick2019-08-231-6/+8
| | | | | | | | | | | | | | | | | There can be several root nodes, i.e.: (1) r0 = r1 (2) r2 = r3 (3) branch if (ssa1) We need to make (3) depend on (1) and (2), old code added dependency only for (2), and (1) was kept as root node since there is no branch/discard or store color between two movs. Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
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