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* radeonsi: get rid of evergreen_hw_context.cChristian Koenig2012-09-263-50/+3
* radeonsi: remove unused codeChristian Koenig2012-09-261-19/+0
* radeonsi: start reworking inferred state handlingChristian König2012-09-264-6/+4
* gallium: Add PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE v2Tom Stellard2012-09-251-0/+16
* r600g: Handle multiple kernels in the same program v2Tom Stellard2012-09-255-21/+84
* nv50/ir/ra: Fix register interference tracking.Jay Cornwall2012-09-251-4/+4
* radeon/llvm: Fix instruction encoding for r600 family GPUsTom Stellard2012-09-243-15/+14
* r600g: Set RADEON_FLUSH_KEEP_TILING_FLAGS when emitting compute csTom Stellard2012-09-241-1/+7
* radeon/llvm: support for interpolation intrinsicsVincent Lejeune2012-09-2210-2/+318
* r600g: Fix build with LLVM compilerTom Stellard2012-09-211-1/+1
* r600g: set QUANT_MODE on Cayman tooMarek Olšák2012-09-221-1/+2
* r600g: use CS helpers to emit streamout stateMarek Olšák2012-09-222-33/+14
* r600g: remove initialization of unused loop register tablesMarek Olšák2012-09-222-38/+0
* r600g: remove now-unused SURFACE_BASE_UPDATE logicMarek Olšák2012-09-223-9/+3
* r600g: remove unused CB registers from register listsMarek Olšák2012-09-222-87/+0
* r600g: atomize framebuffer stateMarek Olšák2012-09-2211-868/+664
* r600g: don't snoop context state while building shadersMarek Olšák2012-09-223-28/+43
* radeon/llvm: Handle loads from the constants address space.Tom Stellard2012-09-212-0/+10
* radeon/llvm: Add support for v4f32 stores on R600Tom Stellard2012-09-213-9/+27
* radeon/llvm: Add support for i8 reads on R600Tom Stellard2012-09-213-0/+25
* radeon/llvm: Expand vector fadd and fmul on R600Tom Stellard2012-09-211-0/+3
* radeon/llvm: Add optimization for FP_ROUNDTom Stellard2012-09-212-0/+27
* radeon/llvm: Replace AMDGPU pow intrinsic with the llvm versionTom Stellard2012-09-214-7/+26
* llvmpipe: fix overflow bug in total texture size computationBrian Paul2012-09-201-2/+16
* r600g/llvm: rs780/rs880 are r600 asicsAlex Deucher2012-09-201-2/+2
* r300/compiler: Use precomputed q values in the register allocatorTom Stellard2012-09-191-1/+69
* r300g: Init regalloc state during context creationTom Stellard2012-09-198-155/+204
* r300/compiler: Don't create register classes for inputsTom Stellard2012-09-191-14/+1
* ra: Add q_values parameter to ra_set_finalize()Tom Stellard2012-09-191-1/+1
* r600g: Invalidate texture cache when creating vertex buffers for compute v2Tom Stellard2012-09-191-1/+3
* r600g: Use LOOP_START_DX10 for loopsTom Stellard2012-09-193-2/+11
* r600g: Set the correct value of COLOR*_DIM for RATsTom Stellard2012-09-191-2/+2
* r600g: Make sure to initialize DB_DEPTH_CONTROL register for computeTom Stellard2012-09-191-1/+3
* r600g: Add some comments and debug printfs to compute codeTom Stellard2012-09-192-5/+53
* r600g: Add missing break to case statementTom Stellard2012-09-191-0/+1
* radeon/llvm: Emit ISA for ALU instructions in the R600 code emitterMichal Sciubidlo2012-09-1910-167/+359
* radeon/llvm: Only support 512 constant registers on R600Tom Stellard2012-09-191-1/+1
* radeon/llvm: Add a fdiv pattern.Vincent Lejeune2012-09-181-3/+10
* radeon/llvm: reserve also corresponding 128bits regVincent Lejeune2012-09-181-0/+1
* softpipe: implement the new can_create_resource() functionBrian Paul2012-09-172-5/+29
* llvmpipe: implement the new can_create_resource() functionBrian Paul2012-09-171-5/+23
* llvmpipe: set max cube texture size to 4K x 4KBrian Paul2012-09-172-1/+2
* radeon/llvm: Inital flow control support for SITom Stellard2012-09-177-2/+168
* r600g: Close a memory leak of llvm byte streamsXinya Zhang2012-09-171-0/+1
* radeon/llvm: Fix unused variable warningTom Stellard2012-09-171-1/+0
* radeon/llvm: Move kernel arg lowering into R600TargetLowering classTom Stellard2012-09-176-470/+35
* radeon/llvm: Match integer add/sub for SI.Michel Dänzer2012-09-171-2/+8
* radeon/llvm: Complete integer comparison patterns for SI.Michel Dänzer2012-09-171-4/+12
* radeon/llvm: Match AMDGPUfract on SI.Michel Dänzer2012-09-171-1/+3
* radeon/llvm: Match int_AMDGPU_floor for SI.Michel Dänzer2012-09-171-1/+3
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