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* radeon/llvm: Use amdgcn triple for SI+ on LLVM >= 3.6Tom Stellard2015-01-064-16/+27
* radeonsi: Cache LLVMTargetMachine object in si_screenTom Stellard2015-01-066-26/+51
* nvc0: add name to magic numberIlia Mirkin2015-01-051-2/+2
* nvc0: regenerate rnndb headersIlia Mirkin2015-01-0517-837/+1157
* nv50: regenerate rnndb headersIlia Mirkin2015-01-0511-358/+451
* nv50: enable texture compressionTobias Klausmann2015-01-052-3/+26
* nv50/ir: enable sat modifier for OP_SUBIlia Mirkin2015-01-051-1/+1
* nv50/ir: Add sat modifier for mulRoy Spliet2015-01-052-1/+7
* nv50,nvc0: avoid doing work inside of an assertIlia Mirkin2015-01-052-2/+4
* nv50/ir: fix texture offsets in release buildsIlia Mirkin2015-01-052-2/+4
* r300g: handle vertex format PIPE_FORMAT_NONEMarek Olšák2015-01-041-2/+11
* nv50/ir: Fold sat into madRoy Spliet2015-01-011-1/+1
* nv50/ir: fold MAD when one of the multiplicands is constIlia Mirkin2015-01-011-0/+23
* radeonsi: fix warningsMarek Olšák2015-01-012-1/+3
* vc4: Fix memory leak as of 0404e7fe0ac2a6234a11290b4b1596e8bc127a4b.Eric Anholt2014-12-311-5/+5
* nv50,nvc0: set vertex id base to index_biasIlia Mirkin2014-12-305-7/+35
* nv50,nvc0: implement half_pixel_centerTiziano Bacocco2014-12-308-14/+11
* vc4: Only render tiles where the scissor ever intersected them.Eric Anholt2014-12-304-10/+52
* vc4: Move draw call reset handling to a helper function.Eric Anholt2014-12-301-23/+31
* vc4: Drop the content of vc4_flush_resource().Eric Anholt2014-12-301-4/+4
* vc4: Handle unaligned accesses in CL emits.Eric Anholt2014-12-252-26/+78
* vc4: Don't bother zero-initializing the shader reloc indices.Eric Anholt2014-12-251-2/+2
* vc4: Fix the argument type for cl_u16().Eric Anholt2014-12-251-1/+1
* radeonsi: Don't modify PA_SC_RASTER_CONFIG register value if rb_mask == 0Michel Dänzer2014-12-251-2/+4
* vc4: Optimize CL emits by doing size checks up front.Eric Anholt2014-12-245-16/+66
* vc4: Avoid repeated hindex lookups in the loop over tiles.Eric Anholt2014-12-242-15/+24
* freedreno/ir3: split out legalize passRob Clark2014-12-235-154/+214
* freedreno/ir3: ra debugRob Clark2014-12-233-17/+61
* radeonsi: force NaNs to 0Marek Olšák2014-12-211-4/+8
* r300g: implement ARR opcodeDavid Heidelberg2014-12-214-4/+16
* freedreno/a4xx: blend-colorRob Clark2014-12-201-0/+13
* freedreno/a4xx: alpha-testRob Clark2014-12-201-0/+2
* freedreno: update generated headersRob Clark2014-12-206-61/+151
* freedreno/ir3: trans_kill cleanupRob Clark2014-12-201-12/+7
* freedreno/ir3: hack for standalone compilerRob Clark2014-12-201-1/+5
* vc4: Coalesce MOVs into VPM with the instructions generating the values.Eric Anholt2014-12-184-15/+143
* vc4: Redefine VPM writes as a (destination) QIR register file.Eric Anholt2014-12-173-7/+19
* vc4: Add support for turning constant uniforms into small immediates.Eric Anholt2014-12-1713-46/+283
* vc4: Move follow_movs() to common QIR code.Eric Anholt2014-12-173-11/+12
* vc4: Fix missing newline for load immediate instruction disasm.Eric Anholt2014-12-171-4/+4
* vc4: Add a userspace BO cache.Eric Anholt2014-12-174-4/+175
* vc4: Add dmabuf support.Eric Anholt2014-12-173-24/+73
* vc4: Drop a weird argument in the BOs-from-handles API.Eric Anholt2014-12-173-7/+5
* vc4: Add support for turning add-based MOVs to muls for pairing.Eric Anholt2014-12-161-2/+49
* vc4: Add a helper for changing a field in an instruction.Eric Anholt2014-12-162-11/+12
* vc4: Fix the name of qpu_waddr_ignores_ws().Eric Anholt2014-12-161-5/+5
* vc4: Add support for enabling early Z discards.Eric Anholt2014-12-161-0/+18
* nvc0: add missed PIPE_CAP_VERTEXID_NOBASEIlia Mirkin2014-12-151-0/+1
* gallium: add TGSI_SEMANTIC_VERTEXID_NOBASE and TGSI_SEMANTIC_BASEVERTEXRoland Scheidegger2014-12-1612-0/+15
* r600g/sb: implement r600 gpr index workaround. (v3.1)Dave Airlie2014-12-164-9/+57
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