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* nv50,nvc0: fix depth range when halfz is enabledIlia Mirkin2016-08-142-4/+14
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97231 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.2 12.0" <[email protected]>
* freedreno/a3xx+a4xx: move common VBOs to fd_contextRob Clark2016-08-1310-185/+116
| | | | | | | | These are the same for a3xx and later. (a2xx could probably use them too, but due to limited hw support and ancient downstream kernels, it isn't so easy to test.) Signed-off-by: Rob Clark <[email protected]>
* freedreno/a2xx: add missing casts to silence notices[email protected]2016-08-131-2/+2
| | | | | Signed-off-by: Francesco Ansanelli <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix issue with emit_tex()Rob Clark2016-08-131-19/+28
| | | | | | | | | | | | | | For various tex fetch instructions, coord's get fixed up in different ways. But modifying the array returned from get_src() has side-effects if the same SSA src is used again.. the later instruction will see the previous fixups. Fix this, and const'ify things to prevent this sort of mistake in the future. Noticed by Varad when adding support for txf_ms. Signed-off-by: Rob Clark <[email protected]>
* swr: [rasterizer core] unused variable warning fixesTim Rowley2016-08-103-12/+0
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer jitter] add core string to JitManagerTim Rowley2016-08-104-6/+10
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] fix OOB check of viewport indicesTim Rowley2016-08-101-2/+2
| | | | | | Use correct comparison intrinsic for OOB check of viewport indices. Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer common] add linux definition for InterlockedAdd64Tim Rowley2016-08-101-0/+2
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer jitter] add VMASKSTOREPS intrinsicTim Rowley2016-08-101-0/+1
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer jitter] add mask support for odd format fetchTim Rowley2016-08-101-15/+26
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] routing of viewport indexes through frontendTim Rowley2016-08-106-27/+91
| | | | | | Viewport transform performed based on per-prim viewport index if available. Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] split FE and BE statsTim Rowley2016-08-1011-59/+95
| | | | | | | | | | | Separated FE stats out into its own structure. There are 17 FE vs 3 BE stat fields. Since there is only one FE thread per DC then we don't have to loop over all threads and sum up FE stats over all the worker threads. This also reduces size of DC since we only need to store one copy of the FE stats and not one per worker. Finally, we can use the new FE callback mechanism to update these. Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] remove all old stats codeTim Rowley2016-08-107-92/+0
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] viewport array supportTim Rowley2016-08-108-34/+49
| | | | | | Change viewport matrix storage from AOS to SOA to support viewport arrays. Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer jitter] fetch support for offsetting VertexIDTim Rowley2016-08-102-4/+16
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] fundamentally change how stats workTim Rowley2016-08-107-19/+94
| | | | | | Add a per draw stats callback to update driver stats. Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] add rasterizerSampleCount to PS contextTim Rowley2016-08-102-0/+6
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] remove cygwin threads.cpp stubsTim Rowley2016-08-101-14/+0
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] allow override of KNOB thread settingsTim Rowley2016-08-106-70/+53
| | | | | | | | - Remove HYPERTHREADED_FE support - Add threading info as optional data passed to SwrCreateContext. If supplied this data will override any KNOB thread settings. Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] add SwrWaitForIdleFETim Rowley2016-08-104-14/+51
| | | | | | | This is a blocking call that waits until all FE work is complete. This is useful for waiting for FE work to complete such as for streamout. Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] change threadsDone to be a 32-bit value.Tim Rowley2016-08-103-5/+5
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] update trivial accept test conditionsTim Rowley2016-08-101-3/+6
| | | | | | | enable/disable raster tile trivial accept test based on scissor enable trait. Can be optimized further. Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] improve implementation for SoWriteOffsetTim Rowley2016-08-108-31/+63
| | | | | | | 1. SoWriteOffset is no longer treated as a stat 2. Added callback from core to update streamout write offset Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer common] make disabled asserts always print (but not break)Tim Rowley2016-08-101-5/+3
| | | | Signed-off-by: Tim Rowley <[email protected]>
* radeonsi: set CB_COLORn_INFO.ROUND_MODEMarek Olšák2016-08-101-0/+5
| | | | | | | just do what the register spec says Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* radeonsi: set CB_COLORn_INFO.SIMPLE_FLOATMarek Olšák2016-08-101-0/+1
| | | | | | | | This can help enable some blend optimizations (see the register spec). Vulkan always sets this. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* radeonsi: disallow MIN/MAX blend equations for dual source blendingMarek Olšák2016-08-101-0/+10
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* radeonsi: only set dual source blending for MRT0Marek Olšák2016-08-101-0/+4
| | | | | | | | | | | | | | This is the proper fix for Overlord and Witcher 2 hangs. The hang condition is that 1 app must write to MRT0 and MRT1 from a pixel shader while MRT1 is disabled in CB_TARGET_MASK (does this generate unflushable pixel quads? I don't know), and another app (e.g. Glamor) must enable dual source blending in both MRT0 and MRT1. The hw gets confused, which leads to corruption and hangs. Cc: 12.0 11.2 <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* gallium/radeon: use unflushed fences for deferred flushes (v2)Marek Olšák2016-08-101-1/+43
| | | | | | | | | | +23% Bioshock Infinite performance. v2: - use the new fence_finish interface - allow deferred fences with multiple contexts - clear the ctx pointer after a deferred flush Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add a pipe_context parameter to fence_finishMarek Olšák2016-08-1027-20/+40
| | | | | | | | required by glClientWaitSync (GL 4.5 Core spec) that can optionally flush the context Reviewed-by: Rob Clark <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add HUD queries for mapped VRAM/GTTMarek Olšák2016-08-102-0/+12
| | | | | | mainly for monitoring visible VRAM congestion Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: track the amount of mapped memoryMarek Olšák2016-08-101-0/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: increase the size of the renderer stringMarek Olšák2016-08-101-1/+1
| | | | | | Mine is longer than 64 bytes. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: implement ARB_clear_texture (v3)Marek Olšák2016-08-103-2/+69
| | | | | | | | | | Some ideas copied from Jakob Sinclair's implementation, but the color clearing is completely different. v2: remove leftover code, disable conditional rendering disable render condition cleanly Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: handle render_condition_enable for clear_rt/dsMarek Olšák2016-08-103-6/+12
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add render_condition_enable param to clear_render_target/depth_stencilMarek Olšák2016-08-1018-47/+91
| | | | | Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enable multi-draw related pipe capsNicolai Hähnle2016-08-091-3/+5
| | | | | | | | | | | | | This enables GL_shader_draw_parameters and GL_ARB_indirect_parameters as well as a properly accelerated implementation of GL_ARB_multi_draw_indirect. Enabling the feature requires a sufficiently uptodate firmware -- those have already been released a long time ago, although this does mean that the feature only works with the amdgpu kernel module, since the radeon module doesn't have a way to query the firmware version. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: program additional multi draw parametersNicolai Hähnle2016-08-091-5/+25
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: program the DRAWID SGPRNicolai Hähnle2016-08-092-4/+7
| | | | | | | | | | Note that for indirect draws, the new MULTI firmware packets are required. There's also no need to reset last_{start_instance,sh_base_reg}, since resetting last_base_vertex is sufficient. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add DRAWID parameter to vertex shadersNicolai Hähnle2016-08-092-2/+10
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: wire up TGSI_SEMANTIC_BASEINSTANCENicolai Hähnle2016-08-091-0/+5
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: remove an incorrect assertionNicolai Hähnle2016-08-091-2/+0
| | | | | | | | | Byte indices don't need any alignment, so remove this assertion (it got moved into a path where a piglit test hit it during the refactoring of commit 64ff23a58c). Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: flush TC L2 cache for indirect draw dataNicolai Hähnle2016-08-092-4/+9
| | | | | | | | | This fixes a bug when indirect draw data is generated by transform feedback. Cc: [email protected] Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/sid: add additional bits for the DRAW_(INDEX)_INDIRECT_MULTI packetsNicolai Hähnle2016-08-091-0/+3
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ddebug: dump driver states and shaders for apitrace callsMarek Olšák2016-08-091-1/+4
| | | | | | I think this was an oversight when the PIPE_DUMP flags were added. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add has_draw_indirect_multi flagNicolai Hähnle2016-08-083-1/+14
| | | | | | | | | | Prefer to use DRAW_(INDEX)_INDIRECT_MULTI when available in the firmware. Versions for SI and CI already added as provided by the firmware team, but keep in mind that they won't currently be used since the radeon kernel module has no interface to query the firmware version. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: transpose indirect/index draw dispatchNicolai Hähnle2016-08-081-45/+31
| | | | | | This allows better code sharing for indirect draw calls. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move index buffer calculations in si_emit_draw_packets upNicolai Hähnle2016-08-081-9/+12
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: unify emitting PKT3_SET_BASE for indirect drawsNicolai Hähnle2016-08-081-16/+9
| | | | Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: query ME/PFP/CE firmware versionsNicolai Hähnle2016-08-082-0/+6
| | | | | | | The radeon kernel module doesn't have the firmware query interface, so the corresponding values will remain 0. Reviewed-by: Marek Olšák <[email protected]>
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