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* freedreno/ir3: array reworkRob Clark2016-01-169-363/+365
* freedreno/ir3: refactor/simplify cpRob Clark2016-01-161-87/+82
* freedreno/ir3: fix incorrect decoding of mov instructionsRob Clark2016-01-161-1/+1
* freedreno/ir3: remove unused tgsi tokens ptrRob Clark2016-01-161-1/+0
* freedreno/ir3: bit of ra refactorRob Clark2016-01-161-25/+20
* freedreno/ir3: cosmetic de-indentRob Clark2016-01-161-36/+34
* nv50/ir: add saturate support on ex2Ilia Mirkin2016-01-162-0/+6
* llvmpipe: ditch additional ref counting for vertex/geometry sampler viewsRoland Scheidegger2016-01-154-46/+12
* llvmpipe: fix "leaking" texturesRoland Scheidegger2016-01-152-2/+9
* nv50/ir: rebase indirect temp arrays to 0, so that we use less lmem spaceIlia Mirkin2016-01-141-14/+44
* nv50/ir: only use FILE_LOCAL_MEMORY for temp arrays that use indirectionIlia Mirkin2016-01-141-15/+50
* nvc0/ir: be careful about propagating very large offsets into const loadIlia Mirkin2016-01-144-1/+19
* nvc0: allow fragment shader inputs to use indirect indexingIlia Mirkin2016-01-141-1/+1
* radeonsi: don't miss changes to SPI_TMPRING_SIZEMarek Olšák2016-01-141-2/+7
* svga: add DXGenMips command supportCharmaine Lee2016-01-1410-26/+144
* svga: add num-generate-mipmap HUD queryCharmaine Lee2016-01-143-1/+12
* gallium/st: add pipe_context::generate_mipmap()Charmaine Lee2016-01-1415-0/+51
* gallium/radeon: do not reallocate user memory buffersNicolai Hähnle2016-01-142-8/+31
* gallium/radeon: implement PIPE_CAP_INVALIDATE_BUFFERNicolai Hähnle2016-01-145-9/+22
* gallium/radeon: reset valid_buffer_range on PIPE_TRANSFER_DISCARD_WHOLE_RESOURCENicolai Hähnle2016-01-141-0/+3
* gallium: add PIPE_CAP_INVALIDATE_BUFFERNicolai Hähnle2016-01-1414-0/+14
* radeonsi: move POSITION and FACE fragment shader inputs to system valuesMarek Olšák2016-01-133-45/+25
* radeonsi: simplify gl_FragCoord behaviorMarek Olšák2016-01-131-23/+22
* llvmpipe: (trivial) use cast wrapper for __m128d to __m128 castsRoland Scheidegger2016-01-131-2/+2
* llvmpipe: avoid most 64 bit math in rasterizationRoland Scheidegger2016-01-132-65/+143
* llvmpipe: scale up bounding box planes to subpixel precisionRoland Scheidegger2016-01-133-30/+30
* llvmpipe: add sse code for fixed position calculationRoland Scheidegger2016-01-131-8/+50
* nvc0: do not force re-binding of compute constbufs on FermiSamuel Pitoiset2016-01-121-1/+1
* nvc0: remove useless goto in nvc0_launch_grid()Samuel Pitoiset2016-01-121-6/+4
* nv50/ir: the whole point of data array is to hand out regular registersIlia Mirkin2016-01-111-1/+1
* nv50/ir: Fix scratch allocation size and filePierre Moreau2016-01-092-3/+3
* nv50,nvc0: use a face sysval to avoid the useless back-and-forth conversionIlia Mirkin2016-01-085-9/+2
* freedreno: add ir3_compiler to gitignoreIlia Mirkin2016-01-081-0/+1
* gallium: add PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENTIlia Mirkin2016-01-0814-13/+27
* gallium: add PIPE_SHADER_CAP_MAX_SHADER_BUFFERSIlia Mirkin2016-01-089-0/+16
* tgsi: add ureg support for image declsIlia Mirkin2016-01-083-7/+15
* util/pstipple: allow fragment shader POSITION to be a system valueMarek Olšák2016-01-084-4/+8
* gallium: add caps for POSITION and FACE system valuesMarek Olšák2016-01-0814-0/+28
* radeon, si: Use TGSI chan name defines in lp_build_emit_fetch() callsEdward O'Callaghan2016-01-082-8/+8
* nvc0: add ARB_indirect_parameters supportIlia Mirkin2016-01-075-6/+313
* nvc0: add support for real ARB_multi_draw_indirectIlia Mirkin2016-01-074-18/+47
* nvc0: adjust indirect draw macros to handle multiple draws at onceIlia Mirkin2016-01-073-52/+101
* gallium: add caps to expose support for multi indirect drawsIlia Mirkin2016-01-0714-0/+28
* llvmpipe: do 64bit plane calculations in the sse pathRoland Scheidegger2016-01-082-50/+70
* llvmpipe: don't store eo as 64bit intRoland Scheidegger2016-01-084-11/+16
* llvmpipe: use aligned data for the assembly program in setupRoland Scheidegger2016-01-081-17/+21
* radeonsi: adjust the parameters of si_shader_dumpMarek Olšák2016-01-073-20/+11
* radeonsi: move si_shader_dump call out of si_compile_llvmMarek Olšák2016-01-072-2/+11
* radeonsi: inline si_shader_binary_readMarek Olšák2016-01-073-11/+3
* radeonsi: move si_shader_dump call out of si_shader_binary_readMarek Olšák2016-01-073-20/+21
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